1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 24 #endif 25 /* --------------------------------------------------------------- */ 26 27 void get_sys_info(sys_info_t *sys_info) 28 { 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 #ifdef CONFIG_FSL_IFC 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 32 u32 ccr; 33 #endif 34 #ifdef CONFIG_FSL_CORENET 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 36 unsigned int cpu; 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 39 #endif 40 41 const u8 core_cplx_PLL[16] = { 42 [ 0] = 0, /* CC1 PPL / 1 */ 43 [ 1] = 0, /* CC1 PPL / 2 */ 44 [ 2] = 0, /* CC1 PPL / 4 */ 45 [ 4] = 1, /* CC2 PPL / 1 */ 46 [ 5] = 1, /* CC2 PPL / 2 */ 47 [ 6] = 1, /* CC2 PPL / 4 */ 48 [ 8] = 2, /* CC3 PPL / 1 */ 49 [ 9] = 2, /* CC3 PPL / 2 */ 50 [10] = 2, /* CC3 PPL / 4 */ 51 [12] = 3, /* CC4 PPL / 1 */ 52 [13] = 3, /* CC4 PPL / 2 */ 53 [14] = 3, /* CC4 PPL / 4 */ 54 }; 55 56 const u8 core_cplx_pll_div[16] = { 57 [ 0] = 1, /* CC1 PPL / 1 */ 58 [ 1] = 2, /* CC1 PPL / 2 */ 59 [ 2] = 4, /* CC1 PPL / 4 */ 60 [ 4] = 1, /* CC2 PPL / 1 */ 61 [ 5] = 2, /* CC2 PPL / 2 */ 62 [ 6] = 4, /* CC2 PPL / 4 */ 63 [ 8] = 1, /* CC3 PPL / 1 */ 64 [ 9] = 2, /* CC3 PPL / 2 */ 65 [10] = 4, /* CC3 PPL / 4 */ 66 [12] = 1, /* CC4 PPL / 1 */ 67 [13] = 2, /* CC4 PPL / 2 */ 68 [14] = 4, /* CC4 PPL / 4 */ 69 }; 70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 72 uint rcw_tmp; 73 #endif 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 76 uint mem_pll_rat; 77 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 78 uint single_src; 79 #endif 80 81 sys_info->freq_systembus = sysclk; 82 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 83 /* 84 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS 85 * are driven by separate DDR Refclock or single source 86 * differential clock. 87 */ 88 single_src = (in_be32(&gur->rcwsr[5]) >> 89 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & 90 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; 91 /* 92 * For single source clocking, both ddrclock and syclock 93 * are driven by differential sysclock. 94 */ 95 if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) { 96 printf("Single Source Clock Configuration\n"); 97 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; 98 } else 99 #endif 100 #ifdef CONFIG_DDR_CLK_FREQ 101 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 102 #else 103 sys_info->freq_ddrbus = sysclk; 104 #endif 105 106 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 107 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 108 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 109 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 110 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 111 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 112 * it uses 6. 113 */ 114 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 115 if (SVR_MAJ(get_svr()) >= 2) 116 mem_pll_rat *= 2; 117 #endif 118 if (mem_pll_rat > 2) 119 sys_info->freq_ddrbus *= mem_pll_rat; 120 else 121 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 122 123 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 124 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 125 if (ratio[i] > 4) 126 freq_c_pll[i] = sysclk * ratio[i]; 127 else 128 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 129 } 130 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 131 /* 132 * As per CHASSIS2 architeture total 12 clusters are posible and 133 * Each cluster has up to 4 cores, sharing the same PLL selection. 134 * The cluster clock assignment is SoC defined. 135 * 136 * Total 4 clock groups are possible with 3 PLLs each. 137 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 138 * clock group B has 3, 4, 6 and so on. 139 * 140 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 141 * depends upon the SoC architeture. Same applies to other 142 * clock groups and clusters. 143 * 144 */ 145 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 146 int cluster = fsl_qoriq_core_to_cluster(cpu); 147 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 148 & 0xf; 149 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 150 cplx_pll += cc_group[cluster] - 1; 151 sys_info->freq_processor[cpu] = 152 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 153 } 154 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \ 155 defined(CONFIG_PPC_T2081) 156 #define FM1_CLK_SEL 0xe0000000 157 #define FM1_CLK_SHIFT 29 158 #else 159 #define PME_CLK_SEL 0xe0000000 160 #define PME_CLK_SHIFT 29 161 #define FM1_CLK_SEL 0x1c000000 162 #define FM1_CLK_SHIFT 26 163 #endif 164 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 165 rcw_tmp = in_be32(&gur->rcwsr[7]); 166 #endif 167 168 #ifdef CONFIG_SYS_DPAA_PME 169 #ifndef CONFIG_PME_PLAT_CLK_DIV 170 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 171 case 1: 172 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 173 break; 174 case 2: 175 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 176 break; 177 case 3: 178 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 179 break; 180 case 4: 181 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 182 break; 183 case 6: 184 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 185 break; 186 case 7: 187 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 188 break; 189 default: 190 printf("Error: Unknown PME clock select!\n"); 191 case 0: 192 sys_info->freq_pme = sys_info->freq_systembus / 2; 193 break; 194 195 } 196 #else 197 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 198 199 #endif 200 #endif 201 202 #ifdef CONFIG_SYS_DPAA_QBMAN 203 sys_info->freq_qman = sys_info->freq_systembus / 2; 204 #endif 205 206 #ifdef CONFIG_SYS_DPAA_FMAN 207 #ifndef CONFIG_FM_PLAT_CLK_DIV 208 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 209 case 1: 210 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 211 break; 212 case 2: 213 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 214 break; 215 case 3: 216 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 217 break; 218 case 4: 219 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 220 break; 221 case 5: 222 sys_info->freq_fman[0] = sys_info->freq_systembus; 223 break; 224 case 6: 225 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 226 break; 227 case 7: 228 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 229 break; 230 default: 231 printf("Error: Unknown FMan1 clock select!\n"); 232 case 0: 233 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 234 break; 235 } 236 #if (CONFIG_SYS_NUM_FMAN) == 2 237 #ifdef CONFIG_SYS_FM2_CLK 238 #define FM2_CLK_SEL 0x00000038 239 #define FM2_CLK_SHIFT 3 240 rcw_tmp = in_be32(&gur->rcwsr[15]); 241 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 242 case 1: 243 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 244 break; 245 case 2: 246 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 247 break; 248 case 3: 249 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 250 break; 251 case 4: 252 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 253 break; 254 case 5: 255 sys_info->freq_fman[1] = sys_info->freq_systembus; 256 break; 257 case 6: 258 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 259 break; 260 case 7: 261 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 262 break; 263 default: 264 printf("Error: Unknown FMan2 clock select!\n"); 265 case 0: 266 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 267 break; 268 } 269 #endif 270 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 271 #else 272 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 273 #endif 274 #endif 275 276 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 277 278 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 279 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 280 & 0xf; 281 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 282 283 sys_info->freq_processor[cpu] = 284 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 285 } 286 #define PME_CLK_SEL 0x80000000 287 #define FM1_CLK_SEL 0x40000000 288 #define FM2_CLK_SEL 0x20000000 289 #define HWA_ASYNC_DIV 0x04000000 290 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 291 #define HWA_CC_PLL 1 292 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 293 #define HWA_CC_PLL 2 294 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 295 #define HWA_CC_PLL 2 296 #else 297 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 298 #endif 299 rcw_tmp = in_be32(&gur->rcwsr[7]); 300 301 #ifdef CONFIG_SYS_DPAA_PME 302 if (rcw_tmp & PME_CLK_SEL) { 303 if (rcw_tmp & HWA_ASYNC_DIV) 304 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 305 else 306 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 307 } else { 308 sys_info->freq_pme = sys_info->freq_systembus / 2; 309 } 310 #endif 311 312 #ifdef CONFIG_SYS_DPAA_FMAN 313 if (rcw_tmp & FM1_CLK_SEL) { 314 if (rcw_tmp & HWA_ASYNC_DIV) 315 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 316 else 317 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 318 } else { 319 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 320 } 321 #if (CONFIG_SYS_NUM_FMAN) == 2 322 if (rcw_tmp & FM2_CLK_SEL) { 323 if (rcw_tmp & HWA_ASYNC_DIV) 324 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 325 else 326 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 327 } else { 328 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 329 } 330 #endif 331 #endif 332 333 #ifdef CONFIG_SYS_DPAA_QBMAN 334 sys_info->freq_qman = sys_info->freq_systembus / 2; 335 #endif 336 337 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 338 339 #else /* CONFIG_FSL_CORENET */ 340 uint plat_ratio, e500_ratio, half_freq_systembus; 341 int i; 342 #ifdef CONFIG_QE 343 __maybe_unused u32 qe_ratio; 344 #endif 345 346 plat_ratio = (gur->porpllsr) & 0x0000003e; 347 plat_ratio >>= 1; 348 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 349 350 /* Divide before multiply to avoid integer 351 * overflow for processor speeds above 2GHz */ 352 half_freq_systembus = sys_info->freq_systembus/2; 353 for (i = 0; i < cpu_numcores(); i++) { 354 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 355 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 356 } 357 358 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 359 sys_info->freq_ddrbus = sys_info->freq_systembus; 360 361 #ifdef CONFIG_DDR_CLK_FREQ 362 { 363 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 364 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 365 if (ddr_ratio != 0x7) 366 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 367 } 368 #endif 369 370 #ifdef CONFIG_QE 371 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 372 sys_info->freq_qe = sys_info->freq_systembus; 373 #else 374 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 375 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 376 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 377 #endif 378 #endif 379 380 #ifdef CONFIG_SYS_DPAA_FMAN 381 sys_info->freq_fman[0] = sys_info->freq_systembus; 382 #endif 383 384 #endif /* CONFIG_FSL_CORENET */ 385 386 #if defined(CONFIG_FSL_LBC) 387 uint lcrr_div; 388 #if defined(CONFIG_SYS_LBC_LCRR) 389 /* We will program LCRR to this value later */ 390 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 391 #else 392 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 393 #endif 394 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 395 #if defined(CONFIG_FSL_CORENET) 396 /* If this is corenet based SoC, bit-representation 397 * for four times the clock divider values. 398 */ 399 lcrr_div *= 4; 400 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 401 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 402 /* 403 * Yes, the entire PQ38 family use the same 404 * bit-representation for twice the clock divider values. 405 */ 406 lcrr_div *= 2; 407 #endif 408 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 409 } else { 410 /* In case anyone cares what the unknown value is */ 411 sys_info->freq_localbus = lcrr_div; 412 } 413 #endif 414 415 #if defined(CONFIG_FSL_IFC) 416 ccr = in_be32(&ifc_regs->ifc_ccr); 417 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 418 419 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 420 #endif 421 } 422 423 424 int get_clocks (void) 425 { 426 sys_info_t sys_info; 427 #ifdef CONFIG_MPC8544 428 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 429 #endif 430 #if defined(CONFIG_CPM2) 431 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 432 uint sccr, dfbrg; 433 434 /* set VCO = 4 * BRG */ 435 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 436 sccr = cpm->im_cpm_intctl.sccr; 437 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 438 #endif 439 get_sys_info (&sys_info); 440 gd->cpu_clk = sys_info.freq_processor[0]; 441 gd->bus_clk = sys_info.freq_systembus; 442 gd->mem_clk = sys_info.freq_ddrbus; 443 gd->arch.lbc_clk = sys_info.freq_localbus; 444 445 #ifdef CONFIG_QE 446 gd->arch.qe_clk = sys_info.freq_qe; 447 gd->arch.brg_clk = gd->arch.qe_clk / 2; 448 #endif 449 /* 450 * The base clock for I2C depends on the actual SOC. Unfortunately, 451 * there is no pattern that can be used to determine the frequency, so 452 * the only choice is to look up the actual SOC number and use the value 453 * for that SOC. This information is taken from application note 454 * AN2919. 455 */ 456 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 457 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 458 defined(CONFIG_P1022) 459 gd->arch.i2c1_clk = sys_info.freq_systembus; 460 #elif defined(CONFIG_MPC8544) 461 /* 462 * On the 8544, the I2C clock is the same as the SEC clock. This can be 463 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 464 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 465 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 466 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 467 */ 468 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 469 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 470 else 471 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 472 #else 473 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 474 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 475 #endif 476 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 477 478 #if defined(CONFIG_FSL_ESDHC) 479 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 480 defined(CONFIG_P1014) 481 gd->arch.sdhc_clk = gd->bus_clk; 482 #else 483 gd->arch.sdhc_clk = gd->bus_clk / 2; 484 #endif 485 #endif /* defined(CONFIG_FSL_ESDHC) */ 486 487 #if defined(CONFIG_CPM2) 488 gd->arch.vco_out = 2*sys_info.freq_systembus; 489 gd->arch.cpm_clk = gd->arch.vco_out / 2; 490 gd->arch.scc_clk = gd->arch.vco_out / 4; 491 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 492 #endif 493 494 if(gd->cpu_clk != 0) return (0); 495 else return (1); 496 } 497 498 499 /******************************************** 500 * get_bus_freq 501 * return system bus freq in Hz 502 *********************************************/ 503 ulong get_bus_freq (ulong dummy) 504 { 505 return gd->bus_clk; 506 } 507 508 /******************************************** 509 * get_ddr_freq 510 * return ddr bus freq in Hz 511 *********************************************/ 512 ulong get_ddr_freq (ulong dummy) 513 { 514 return gd->mem_clk; 515 } 516