1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 24 #endif 25 /* --------------------------------------------------------------- */ 26 27 void get_sys_info(sys_info_t *sys_info) 28 { 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 #ifdef CONFIG_FSL_IFC 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 32 u32 ccr; 33 #endif 34 #ifdef CONFIG_FSL_CORENET 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 36 unsigned int cpu; 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 39 #endif 40 __maybe_unused u32 svr; 41 42 const u8 core_cplx_PLL[16] = { 43 [ 0] = 0, /* CC1 PPL / 1 */ 44 [ 1] = 0, /* CC1 PPL / 2 */ 45 [ 2] = 0, /* CC1 PPL / 4 */ 46 [ 4] = 1, /* CC2 PPL / 1 */ 47 [ 5] = 1, /* CC2 PPL / 2 */ 48 [ 6] = 1, /* CC2 PPL / 4 */ 49 [ 8] = 2, /* CC3 PPL / 1 */ 50 [ 9] = 2, /* CC3 PPL / 2 */ 51 [10] = 2, /* CC3 PPL / 4 */ 52 [12] = 3, /* CC4 PPL / 1 */ 53 [13] = 3, /* CC4 PPL / 2 */ 54 [14] = 3, /* CC4 PPL / 4 */ 55 }; 56 57 const u8 core_cplx_pll_div[16] = { 58 [ 0] = 1, /* CC1 PPL / 1 */ 59 [ 1] = 2, /* CC1 PPL / 2 */ 60 [ 2] = 4, /* CC1 PPL / 4 */ 61 [ 4] = 1, /* CC2 PPL / 1 */ 62 [ 5] = 2, /* CC2 PPL / 2 */ 63 [ 6] = 4, /* CC2 PPL / 4 */ 64 [ 8] = 1, /* CC3 PPL / 1 */ 65 [ 9] = 2, /* CC3 PPL / 2 */ 66 [10] = 4, /* CC3 PPL / 4 */ 67 [12] = 1, /* CC4 PPL / 1 */ 68 [13] = 2, /* CC4 PPL / 2 */ 69 [14] = 4, /* CC4 PPL / 4 */ 70 }; 71 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 72 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 73 uint rcw_tmp; 74 #endif 75 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 76 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 77 uint mem_pll_rat; 78 79 sys_info->freq_systembus = sysclk; 80 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 81 uint ddr_refclk_sel; 82 unsigned int porsr1_sys_clk; 83 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT 84 & FSL_DCFG_PORSR1_SYSCLK_MASK; 85 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) 86 sys_info->diff_sysclk = 1; 87 else 88 sys_info->diff_sysclk = 0; 89 90 /* 91 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS 92 * are driven by separate DDR Refclock or single source 93 * differential clock. 94 */ 95 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> 96 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & 97 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; 98 /* 99 * For single source clocking, both ddrclock and sysclock 100 * are driven by differential sysclock. 101 */ 102 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) 103 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; 104 else 105 #endif 106 #ifdef CONFIG_DDR_CLK_FREQ 107 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 108 #else 109 sys_info->freq_ddrbus = sysclk; 110 #endif 111 112 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 113 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 114 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 115 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 116 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 117 if (mem_pll_rat == 0) { 118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 119 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 120 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 121 } 122 #endif 123 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of 124 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 125 * it uses 6. 126 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 127 */ 128 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 129 defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) 130 svr = get_svr(); 131 switch (SVR_SOC_VER(svr)) { 132 case SVR_T4240: 133 case SVR_T4160: 134 case SVR_T4120: 135 case SVR_T4080: 136 if (SVR_MAJ(svr) >= 2) 137 mem_pll_rat *= 2; 138 break; 139 case SVR_T2080: 140 case SVR_T2081: 141 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1)) 142 mem_pll_rat *= 2; 143 break; 144 default: 145 break; 146 } 147 #endif 148 if (mem_pll_rat > 2) 149 sys_info->freq_ddrbus *= mem_pll_rat; 150 else 151 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 152 153 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 154 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 155 if (ratio[i] > 4) 156 freq_c_pll[i] = sysclk * ratio[i]; 157 else 158 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 159 } 160 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 161 /* 162 * As per CHASSIS2 architeture total 12 clusters are posible and 163 * Each cluster has up to 4 cores, sharing the same PLL selection. 164 * The cluster clock assignment is SoC defined. 165 * 166 * Total 4 clock groups are possible with 3 PLLs each. 167 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 168 * clock group B has 3, 4, 6 and so on. 169 * 170 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 171 * depends upon the SoC architeture. Same applies to other 172 * clock groups and clusters. 173 * 174 */ 175 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 176 int cluster = fsl_qoriq_core_to_cluster(cpu); 177 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 178 & 0xf; 179 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 180 cplx_pll += cc_group[cluster] - 1; 181 sys_info->freq_processor[cpu] = 182 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 183 } 184 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \ 185 defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 186 #define FM1_CLK_SEL 0xe0000000 187 #define FM1_CLK_SHIFT 29 188 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) 189 #define FM1_CLK_SEL 0x00000007 190 #define FM1_CLK_SHIFT 0 191 #else 192 #define PME_CLK_SEL 0xe0000000 193 #define PME_CLK_SHIFT 29 194 #define FM1_CLK_SEL 0x1c000000 195 #define FM1_CLK_SHIFT 26 196 #endif 197 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 198 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) 199 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; 200 #else 201 rcw_tmp = in_be32(&gur->rcwsr[7]); 202 #endif 203 #endif 204 205 #ifdef CONFIG_SYS_DPAA_PME 206 #ifndef CONFIG_PME_PLAT_CLK_DIV 207 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 208 case 1: 209 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 210 break; 211 case 2: 212 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 213 break; 214 case 3: 215 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 216 break; 217 case 4: 218 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 219 break; 220 case 6: 221 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 222 break; 223 case 7: 224 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 225 break; 226 default: 227 printf("Error: Unknown PME clock select!\n"); 228 case 0: 229 sys_info->freq_pme = sys_info->freq_systembus / 2; 230 break; 231 232 } 233 #else 234 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 235 236 #endif 237 #endif 238 239 #ifdef CONFIG_SYS_DPAA_QBMAN 240 #ifndef CONFIG_QBMAN_CLK_DIV 241 #define CONFIG_QBMAN_CLK_DIV 2 242 #endif 243 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; 244 #endif 245 246 #ifdef CONFIG_SYS_DPAA_FMAN 247 #ifndef CONFIG_FM_PLAT_CLK_DIV 248 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 249 case 1: 250 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 251 break; 252 case 2: 253 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 254 break; 255 case 3: 256 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 257 break; 258 case 4: 259 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 260 break; 261 case 5: 262 sys_info->freq_fman[0] = sys_info->freq_systembus; 263 break; 264 case 6: 265 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 266 break; 267 case 7: 268 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 269 break; 270 default: 271 printf("Error: Unknown FMan1 clock select!\n"); 272 case 0: 273 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 274 break; 275 } 276 #if (CONFIG_SYS_NUM_FMAN) == 2 277 #ifdef CONFIG_SYS_FM2_CLK 278 #define FM2_CLK_SEL 0x00000038 279 #define FM2_CLK_SHIFT 3 280 rcw_tmp = in_be32(&gur->rcwsr[15]); 281 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 282 case 1: 283 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 284 break; 285 case 2: 286 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 287 break; 288 case 3: 289 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 290 break; 291 case 4: 292 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 293 break; 294 case 5: 295 sys_info->freq_fman[1] = sys_info->freq_systembus; 296 break; 297 case 6: 298 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 299 break; 300 case 7: 301 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 302 break; 303 default: 304 printf("Error: Unknown FMan2 clock select!\n"); 305 case 0: 306 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 307 break; 308 } 309 #endif 310 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 311 #else 312 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 313 #endif 314 #endif 315 316 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 317 318 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 319 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 320 & 0xf; 321 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 322 323 sys_info->freq_processor[cpu] = 324 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 325 } 326 #define PME_CLK_SEL 0x80000000 327 #define FM1_CLK_SEL 0x40000000 328 #define FM2_CLK_SEL 0x20000000 329 #define HWA_ASYNC_DIV 0x04000000 330 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 331 #define HWA_CC_PLL 1 332 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 333 #define HWA_CC_PLL 2 334 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 335 #define HWA_CC_PLL 2 336 #else 337 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 338 #endif 339 rcw_tmp = in_be32(&gur->rcwsr[7]); 340 341 #ifdef CONFIG_SYS_DPAA_PME 342 if (rcw_tmp & PME_CLK_SEL) { 343 if (rcw_tmp & HWA_ASYNC_DIV) 344 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 345 else 346 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 347 } else { 348 sys_info->freq_pme = sys_info->freq_systembus / 2; 349 } 350 #endif 351 352 #ifdef CONFIG_SYS_DPAA_FMAN 353 if (rcw_tmp & FM1_CLK_SEL) { 354 if (rcw_tmp & HWA_ASYNC_DIV) 355 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 356 else 357 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 358 } else { 359 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 360 } 361 #if (CONFIG_SYS_NUM_FMAN) == 2 362 if (rcw_tmp & FM2_CLK_SEL) { 363 if (rcw_tmp & HWA_ASYNC_DIV) 364 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 365 else 366 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 367 } else { 368 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 369 } 370 #endif 371 #endif 372 373 #ifdef CONFIG_SYS_DPAA_QBMAN 374 sys_info->freq_qman = sys_info->freq_systembus / 2; 375 #endif 376 377 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 378 379 #ifdef CONFIG_U_QE 380 sys_info->freq_qe = sys_info->freq_systembus / 2; 381 #endif 382 383 #else /* CONFIG_FSL_CORENET */ 384 uint plat_ratio, e500_ratio, half_freq_systembus; 385 int i; 386 #ifdef CONFIG_QE 387 __maybe_unused u32 qe_ratio; 388 #endif 389 390 plat_ratio = (gur->porpllsr) & 0x0000003e; 391 plat_ratio >>= 1; 392 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 393 394 /* Divide before multiply to avoid integer 395 * overflow for processor speeds above 2GHz */ 396 half_freq_systembus = sys_info->freq_systembus/2; 397 for (i = 0; i < cpu_numcores(); i++) { 398 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 399 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 400 } 401 402 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 403 sys_info->freq_ddrbus = sys_info->freq_systembus; 404 405 #ifdef CONFIG_DDR_CLK_FREQ 406 { 407 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 408 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 409 if (ddr_ratio != 0x7) 410 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 411 } 412 #endif 413 414 #ifdef CONFIG_QE 415 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 416 sys_info->freq_qe = sys_info->freq_systembus; 417 #else 418 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 419 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 420 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 421 #endif 422 #endif 423 424 #ifdef CONFIG_SYS_DPAA_FMAN 425 sys_info->freq_fman[0] = sys_info->freq_systembus; 426 #endif 427 428 #endif /* CONFIG_FSL_CORENET */ 429 430 #if defined(CONFIG_FSL_LBC) 431 uint lcrr_div; 432 #if defined(CONFIG_SYS_LBC_LCRR) 433 /* We will program LCRR to this value later */ 434 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 435 #else 436 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 437 #endif 438 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 439 #if defined(CONFIG_FSL_CORENET) 440 /* If this is corenet based SoC, bit-representation 441 * for four times the clock divider values. 442 */ 443 lcrr_div *= 4; 444 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 445 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 446 /* 447 * Yes, the entire PQ38 family use the same 448 * bit-representation for twice the clock divider values. 449 */ 450 lcrr_div *= 2; 451 #endif 452 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 453 } else { 454 /* In case anyone cares what the unknown value is */ 455 sys_info->freq_localbus = lcrr_div; 456 } 457 #endif 458 459 #if defined(CONFIG_FSL_IFC) 460 ccr = ifc_in32(&ifc_regs->ifc_ccr); 461 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 462 463 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 464 #endif 465 } 466 467 468 int get_clocks (void) 469 { 470 sys_info_t sys_info; 471 #ifdef CONFIG_MPC8544 472 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 473 #endif 474 #if defined(CONFIG_CPM2) 475 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 476 uint sccr, dfbrg; 477 478 /* set VCO = 4 * BRG */ 479 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 480 sccr = cpm->im_cpm_intctl.sccr; 481 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 482 #endif 483 get_sys_info (&sys_info); 484 gd->cpu_clk = sys_info.freq_processor[0]; 485 gd->bus_clk = sys_info.freq_systembus; 486 gd->mem_clk = sys_info.freq_ddrbus; 487 gd->arch.lbc_clk = sys_info.freq_localbus; 488 489 #ifdef CONFIG_QE 490 gd->arch.qe_clk = sys_info.freq_qe; 491 gd->arch.brg_clk = gd->arch.qe_clk / 2; 492 #endif 493 /* 494 * The base clock for I2C depends on the actual SOC. Unfortunately, 495 * there is no pattern that can be used to determine the frequency, so 496 * the only choice is to look up the actual SOC number and use the value 497 * for that SOC. This information is taken from application note 498 * AN2919. 499 */ 500 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 501 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 502 defined(CONFIG_P1022) 503 gd->arch.i2c1_clk = sys_info.freq_systembus; 504 #elif defined(CONFIG_MPC8544) 505 /* 506 * On the 8544, the I2C clock is the same as the SEC clock. This can be 507 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 508 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 509 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 510 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 511 */ 512 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 513 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 514 else 515 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 516 #else 517 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 518 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 519 #endif 520 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 521 522 #if defined(CONFIG_FSL_ESDHC) 523 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 524 defined(CONFIG_P1014) 525 gd->arch.sdhc_clk = gd->bus_clk; 526 #else 527 gd->arch.sdhc_clk = gd->bus_clk / 2; 528 #endif 529 #endif /* defined(CONFIG_FSL_ESDHC) */ 530 531 #if defined(CONFIG_CPM2) 532 gd->arch.vco_out = 2*sys_info.freq_systembus; 533 gd->arch.cpm_clk = gd->arch.vco_out / 2; 534 gd->arch.scc_clk = gd->arch.vco_out / 4; 535 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 536 #endif 537 538 if(gd->cpu_clk != 0) return (0); 539 else return (1); 540 } 541 542 543 /******************************************** 544 * get_bus_freq 545 * return system bus freq in Hz 546 *********************************************/ 547 ulong get_bus_freq (ulong dummy) 548 { 549 return gd->bus_clk; 550 } 551 552 /******************************************** 553 * get_ddr_freq 554 * return ddr bus freq in Hz 555 *********************************************/ 556 ulong get_ddr_freq (ulong dummy) 557 { 558 return gd->mem_clk; 559 } 560