1 /* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Xianghua Xiao, (X.Xiao@motorola.com) 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <ppc_asm.tmpl> 15 #include <linux/compiler.h> 16 #include <asm/processor.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS 23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6 24 #endif 25 /* --------------------------------------------------------------- */ 26 27 void get_sys_info(sys_info_t *sys_info) 28 { 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 30 #ifdef CONFIG_FSL_IFC 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 32 u32 ccr; 33 #endif 34 #ifdef CONFIG_FSL_CORENET 35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); 36 unsigned int cpu; 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; 39 #endif 40 41 const u8 core_cplx_PLL[16] = { 42 [ 0] = 0, /* CC1 PPL / 1 */ 43 [ 1] = 0, /* CC1 PPL / 2 */ 44 [ 2] = 0, /* CC1 PPL / 4 */ 45 [ 4] = 1, /* CC2 PPL / 1 */ 46 [ 5] = 1, /* CC2 PPL / 2 */ 47 [ 6] = 1, /* CC2 PPL / 4 */ 48 [ 8] = 2, /* CC3 PPL / 1 */ 49 [ 9] = 2, /* CC3 PPL / 2 */ 50 [10] = 2, /* CC3 PPL / 4 */ 51 [12] = 3, /* CC4 PPL / 1 */ 52 [13] = 3, /* CC4 PPL / 2 */ 53 [14] = 3, /* CC4 PPL / 4 */ 54 }; 55 56 const u8 core_cplx_pll_div[16] = { 57 [ 0] = 1, /* CC1 PPL / 1 */ 58 [ 1] = 2, /* CC1 PPL / 2 */ 59 [ 2] = 4, /* CC1 PPL / 4 */ 60 [ 4] = 1, /* CC2 PPL / 1 */ 61 [ 5] = 2, /* CC2 PPL / 2 */ 62 [ 6] = 4, /* CC2 PPL / 4 */ 63 [ 8] = 1, /* CC3 PPL / 1 */ 64 [ 9] = 2, /* CC3 PPL / 2 */ 65 [10] = 4, /* CC3 PPL / 4 */ 66 [12] = 1, /* CC4 PPL / 1 */ 67 [13] = 2, /* CC4 PPL / 2 */ 68 [14] = 4, /* CC4 PPL / 4 */ 69 }; 70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; 71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 72 uint rcw_tmp; 73 #endif 74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; 75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ; 76 uint mem_pll_rat; 77 78 sys_info->freq_systembus = sysclk; 79 #ifdef CONFIG_DDR_CLK_FREQ 80 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; 81 #else 82 sys_info->freq_ddrbus = sysclk; 83 #endif 84 85 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 86 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 87 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) 88 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 89 if (mem_pll_rat > 2) 90 sys_info->freq_ddrbus *= mem_pll_rat; 91 else 92 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; 93 94 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { 95 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; 96 if (ratio[i] > 4) 97 freq_c_pll[i] = sysclk * ratio[i]; 98 else 99 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; 100 } 101 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 102 /* 103 * As per CHASSIS2 architeture total 12 clusters are posible and 104 * Each cluster has up to 4 cores, sharing the same PLL selection. 105 * The cluster clock assignment is SoC defined. 106 * 107 * Total 4 clock groups are possible with 3 PLLs each. 108 * as per array indices, clock group A has 0, 1, 2 numbered PLLs & 109 * clock group B has 3, 4, 6 and so on. 110 * 111 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster 112 * depends upon the SoC architeture. Same applies to other 113 * clock groups and clusters. 114 * 115 */ 116 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 117 int cluster = fsl_qoriq_core_to_cluster(cpu); 118 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) 119 & 0xf; 120 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 121 cplx_pll += cc_group[cluster] - 1; 122 sys_info->freq_processor[cpu] = 123 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 124 } 125 #ifdef CONFIG_PPC_B4860 126 #define FM1_CLK_SEL 0xe0000000 127 #define FM1_CLK_SHIFT 29 128 #else 129 #define PME_CLK_SEL 0xe0000000 130 #define PME_CLK_SHIFT 29 131 #define FM1_CLK_SEL 0x1c000000 132 #define FM1_CLK_SHIFT 26 133 #endif 134 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) 135 rcw_tmp = in_be32(&gur->rcwsr[7]); 136 #endif 137 138 #ifdef CONFIG_SYS_DPAA_PME 139 #ifndef CONFIG_PME_PLAT_CLK_DIV 140 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { 141 case 1: 142 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; 143 break; 144 case 2: 145 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; 146 break; 147 case 3: 148 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; 149 break; 150 case 4: 151 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; 152 break; 153 case 6: 154 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; 155 break; 156 case 7: 157 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; 158 break; 159 default: 160 printf("Error: Unknown PME clock select!\n"); 161 case 0: 162 sys_info->freq_pme = sys_info->freq_systembus / 2; 163 break; 164 165 } 166 #else 167 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; 168 169 #endif 170 #endif 171 172 #ifdef CONFIG_SYS_DPAA_QBMAN 173 sys_info->freq_qman = sys_info->freq_systembus / 2; 174 #endif 175 176 #ifdef CONFIG_SYS_DPAA_FMAN 177 #ifndef CONFIG_FM_PLAT_CLK_DIV 178 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { 179 case 1: 180 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; 181 break; 182 case 2: 183 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; 184 break; 185 case 3: 186 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; 187 break; 188 case 4: 189 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; 190 break; 191 case 5: 192 sys_info->freq_fman[0] = sys_info->freq_systembus; 193 break; 194 case 6: 195 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; 196 break; 197 case 7: 198 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; 199 break; 200 default: 201 printf("Error: Unknown FMan1 clock select!\n"); 202 case 0: 203 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 204 break; 205 } 206 #if (CONFIG_SYS_NUM_FMAN) == 2 207 #ifdef CONFIG_SYS_FM2_CLK 208 #define FM2_CLK_SEL 0x00000038 209 #define FM2_CLK_SHIFT 3 210 rcw_tmp = in_be32(&gur->rcwsr[15]); 211 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { 212 case 1: 213 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; 214 break; 215 case 2: 216 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; 217 break; 218 case 3: 219 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; 220 break; 221 case 4: 222 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; 223 break; 224 case 6: 225 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; 226 break; 227 case 7: 228 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; 229 break; 230 default: 231 printf("Error: Unknown FMan2 clock select!\n"); 232 case 0: 233 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 234 break; 235 } 236 #endif 237 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 238 #else 239 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; 240 #endif 241 #endif 242 243 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 244 245 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { 246 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) 247 & 0xf; 248 u32 cplx_pll = core_cplx_PLL[c_pll_sel]; 249 250 sys_info->freq_processor[cpu] = 251 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; 252 } 253 #define PME_CLK_SEL 0x80000000 254 #define FM1_CLK_SEL 0x40000000 255 #define FM2_CLK_SEL 0x20000000 256 #define HWA_ASYNC_DIV 0x04000000 257 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) 258 #define HWA_CC_PLL 1 259 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) 260 #define HWA_CC_PLL 2 261 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) 262 #define HWA_CC_PLL 2 263 #else 264 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case 265 #endif 266 rcw_tmp = in_be32(&gur->rcwsr[7]); 267 268 #ifdef CONFIG_SYS_DPAA_PME 269 if (rcw_tmp & PME_CLK_SEL) { 270 if (rcw_tmp & HWA_ASYNC_DIV) 271 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; 272 else 273 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; 274 } else { 275 sys_info->freq_pme = sys_info->freq_systembus / 2; 276 } 277 #endif 278 279 #ifdef CONFIG_SYS_DPAA_FMAN 280 if (rcw_tmp & FM1_CLK_SEL) { 281 if (rcw_tmp & HWA_ASYNC_DIV) 282 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; 283 else 284 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; 285 } else { 286 sys_info->freq_fman[0] = sys_info->freq_systembus / 2; 287 } 288 #if (CONFIG_SYS_NUM_FMAN) == 2 289 if (rcw_tmp & FM2_CLK_SEL) { 290 if (rcw_tmp & HWA_ASYNC_DIV) 291 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; 292 else 293 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; 294 } else { 295 sys_info->freq_fman[1] = sys_info->freq_systembus / 2; 296 } 297 #endif 298 #endif 299 300 #ifdef CONFIG_SYS_DPAA_QBMAN 301 sys_info->freq_qman = sys_info->freq_systembus / 2; 302 #endif 303 304 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 305 306 #else /* CONFIG_FSL_CORENET */ 307 uint plat_ratio, e500_ratio, half_freq_systembus; 308 int i; 309 #ifdef CONFIG_QE 310 __maybe_unused u32 qe_ratio; 311 #endif 312 313 plat_ratio = (gur->porpllsr) & 0x0000003e; 314 plat_ratio >>= 1; 315 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 316 317 /* Divide before multiply to avoid integer 318 * overflow for processor speeds above 2GHz */ 319 half_freq_systembus = sys_info->freq_systembus/2; 320 for (i = 0; i < cpu_numcores(); i++) { 321 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; 322 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; 323 } 324 325 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ 326 sys_info->freq_ddrbus = sys_info->freq_systembus; 327 328 #ifdef CONFIG_DDR_CLK_FREQ 329 { 330 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 331 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 332 if (ddr_ratio != 0x7) 333 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; 334 } 335 #endif 336 337 #ifdef CONFIG_QE 338 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 339 sys_info->freq_qe = sys_info->freq_systembus; 340 #else 341 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) 342 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; 343 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; 344 #endif 345 #endif 346 347 #ifdef CONFIG_SYS_DPAA_FMAN 348 sys_info->freq_fman[0] = sys_info->freq_systembus; 349 #endif 350 351 #endif /* CONFIG_FSL_CORENET */ 352 353 #if defined(CONFIG_FSL_LBC) 354 uint lcrr_div; 355 #if defined(CONFIG_SYS_LBC_LCRR) 356 /* We will program LCRR to this value later */ 357 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; 358 #else 359 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; 360 #endif 361 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { 362 #if defined(CONFIG_FSL_CORENET) 363 /* If this is corenet based SoC, bit-representation 364 * for four times the clock divider values. 365 */ 366 lcrr_div *= 4; 367 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ 368 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) 369 /* 370 * Yes, the entire PQ38 family use the same 371 * bit-representation for twice the clock divider values. 372 */ 373 lcrr_div *= 2; 374 #endif 375 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; 376 } else { 377 /* In case anyone cares what the unknown value is */ 378 sys_info->freq_localbus = lcrr_div; 379 } 380 #endif 381 382 #if defined(CONFIG_FSL_IFC) 383 ccr = in_be32(&ifc_regs->ifc_ccr); 384 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; 385 386 sys_info->freq_localbus = sys_info->freq_systembus / ccr; 387 #endif 388 } 389 390 391 int get_clocks (void) 392 { 393 sys_info_t sys_info; 394 #ifdef CONFIG_MPC8544 395 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; 396 #endif 397 #if defined(CONFIG_CPM2) 398 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 399 uint sccr, dfbrg; 400 401 /* set VCO = 4 * BRG */ 402 cpm->im_cpm_intctl.sccr &= 0xfffffffc; 403 sccr = cpm->im_cpm_intctl.sccr; 404 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; 405 #endif 406 get_sys_info (&sys_info); 407 gd->cpu_clk = sys_info.freq_processor[0]; 408 gd->bus_clk = sys_info.freq_systembus; 409 gd->mem_clk = sys_info.freq_ddrbus; 410 gd->arch.lbc_clk = sys_info.freq_localbus; 411 412 #ifdef CONFIG_QE 413 gd->arch.qe_clk = sys_info.freq_qe; 414 gd->arch.brg_clk = gd->arch.qe_clk / 2; 415 #endif 416 /* 417 * The base clock for I2C depends on the actual SOC. Unfortunately, 418 * there is no pattern that can be used to determine the frequency, so 419 * the only choice is to look up the actual SOC number and use the value 420 * for that SOC. This information is taken from application note 421 * AN2919. 422 */ 423 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 424 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ 425 defined(CONFIG_P1022) 426 gd->arch.i2c1_clk = sys_info.freq_systembus; 427 #elif defined(CONFIG_MPC8544) 428 /* 429 * On the 8544, the I2C clock is the same as the SEC clock. This can be 430 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See 431 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all 432 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the 433 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. 434 */ 435 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) 436 gd->arch.i2c1_clk = sys_info.freq_systembus / 3; 437 else 438 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 439 #else 440 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ 441 gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 442 #endif 443 gd->arch.i2c2_clk = gd->arch.i2c1_clk; 444 445 #if defined(CONFIG_FSL_ESDHC) 446 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ 447 defined(CONFIG_P1014) 448 gd->arch.sdhc_clk = gd->bus_clk; 449 #else 450 gd->arch.sdhc_clk = gd->bus_clk / 2; 451 #endif 452 #endif /* defined(CONFIG_FSL_ESDHC) */ 453 454 #if defined(CONFIG_CPM2) 455 gd->arch.vco_out = 2*sys_info.freq_systembus; 456 gd->arch.cpm_clk = gd->arch.vco_out / 2; 457 gd->arch.scc_clk = gd->arch.vco_out / 4; 458 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); 459 #endif 460 461 if(gd->cpu_clk != 0) return (0); 462 else return (1); 463 } 464 465 466 /******************************************** 467 * get_bus_freq 468 * return system bus freq in Hz 469 *********************************************/ 470 ulong get_bus_freq (ulong dummy) 471 { 472 return gd->bus_clk; 473 } 474 475 /******************************************** 476 * get_ddr_freq 477 * return ddr bus freq in Hz 478 *********************************************/ 479 ulong get_ddr_freq (ulong dummy) 480 { 481 return gd->mem_clk; 482 } 483