1 /* 2 * (C) Copyright 2003 Motorola Inc. 3 * Xianghua Xiao (X.Xiao@motorola.com) 4 * Modified based on 8260 for 8560. 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00. 28 */ 29 30 /* 31 * Minimal serial functions needed to use one of the SCC ports 32 * as serial console interface. 33 */ 34 35 #include <common.h> 36 #include <asm/cpm_85xx.h> 37 #include <serial.h> 38 #include <linux/compiler.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #if defined(CONFIG_CONS_ON_SCC) 43 44 #if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ 45 46 #define SCC_INDEX 0 47 #define PROFF_SCC PROFF_SCC1 48 #define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ 49 CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) 50 #define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) 51 #define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE 52 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK 53 54 #elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ 55 56 #define SCC_INDEX 1 57 #define PROFF_SCC PROFF_SCC2 58 #define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ 59 CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) 60 #define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) 61 #define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE 62 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK 63 64 #elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ 65 66 #define SCC_INDEX 2 67 #define PROFF_SCC PROFF_SCC3 68 #define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ 69 CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) 70 #define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) 71 #define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE 72 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK 73 74 #elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ 75 76 #define SCC_INDEX 3 77 #define PROFF_SCC PROFF_SCC4 78 #define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ 79 CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) 80 #define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) 81 #define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE 82 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK 83 84 #else 85 86 #error "console not correctly defined" 87 88 #endif 89 90 static int mpc85xx_serial_init(void) 91 { 92 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 93 volatile ccsr_cpm_scc_t *sp; 94 volatile scc_uart_t *up; 95 volatile cbd_t *tbdf, *rbdf; 96 volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); 97 uint dpaddr; 98 99 /* initialize pointers to SCC */ 100 101 sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]); 102 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); 103 104 /* Disable transmitter/receiver. 105 */ 106 sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); 107 108 /* put the SCC channel into NMSI (non multiplexd serial interface) 109 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). 110 */ 111 cpm->im_cpm_mux.cmxscr = \ 112 (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; 113 114 /* Set up the baud rate generator. 115 */ 116 serial_setbrg (); 117 118 /* Allocate space for two buffer descriptors in the DP ram. 119 * damm: allocating space after the two buffers for rx/tx data 120 */ 121 122 dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); 123 124 /* Set the physical address of the host memory buffers in 125 * the buffer descriptors. 126 */ 127 rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]); 128 rbdf->cbd_bufaddr = (uint) (rbdf+2); 129 rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; 130 tbdf = rbdf + 1; 131 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; 132 tbdf->cbd_sc = BD_SC_WRAP; 133 134 /* Set up the uart parameters in the parameter ram. 135 */ 136 up->scc_genscc.scc_rbase = dpaddr; 137 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); 138 up->scc_genscc.scc_rfcr = CPMFCR_EB; 139 up->scc_genscc.scc_tfcr = CPMFCR_EB; 140 up->scc_genscc.scc_mrblr = 1; 141 up->scc_maxidl = 0; 142 up->scc_brkcr = 1; 143 up->scc_parec = 0; 144 up->scc_frmec = 0; 145 up->scc_nosec = 0; 146 up->scc_brkec = 0; 147 up->scc_uaddr1 = 0; 148 up->scc_uaddr2 = 0; 149 up->scc_toseq = 0; 150 up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; 151 up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; 152 up->scc_rccm = 0xc0ff; 153 154 /* Mask all interrupts and remove anything pending. 155 */ 156 sp->sccm = 0; 157 sp->scce = 0xffff; 158 159 /* Set 8 bit FIFO, 16 bit oversampling and UART mode. 160 */ 161 sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ 162 sp->gsmrl = \ 163 SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; 164 165 /* Set CTS no flow control, 1 stop bit, 8 bit character length, 166 * normal async UART mode, no parity 167 */ 168 sp->psmr = SCU_PSMR_CL; 169 170 /* execute the "Init Rx and Tx params" CP command. 171 */ 172 173 while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ 174 ; 175 176 cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, 177 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; 178 179 while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ 180 ; 181 182 /* Enable transmitter/receiver. 183 */ 184 sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; 185 186 return (0); 187 } 188 189 static void mpc85xx_serial_setbrg(void) 190 { 191 #if defined(CONFIG_CONS_USE_EXTC) 192 m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate, 193 CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); 194 #else 195 m8560_cpm_setbrg(SCC_INDEX, gd->baudrate); 196 #endif 197 } 198 199 static void mpc85xx_serial_putc(const char c) 200 { 201 volatile scc_uart_t *up; 202 volatile cbd_t *tbdf; 203 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 204 205 if (c == '\n') 206 serial_putc ('\r'); 207 208 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); 209 tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]); 210 211 /* Wait for last character to go. 212 */ 213 while (tbdf->cbd_sc & BD_SC_READY) 214 ; 215 216 /* Load the character into the transmit buffer. 217 */ 218 *(volatile char *)tbdf->cbd_bufaddr = c; 219 tbdf->cbd_datlen = 1; 220 tbdf->cbd_sc |= BD_SC_READY; 221 } 222 223 static int mpc85xx_serial_getc(void) 224 { 225 volatile cbd_t *rbdf; 226 volatile scc_uart_t *up; 227 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 228 unsigned char c; 229 230 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); 231 rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); 232 233 /* Wait for character to show up. 234 */ 235 while (rbdf->cbd_sc & BD_SC_EMPTY) 236 ; 237 238 /* Grab the char and clear the buffer again. 239 */ 240 c = *(volatile unsigned char *)rbdf->cbd_bufaddr; 241 rbdf->cbd_sc |= BD_SC_EMPTY; 242 243 return (c); 244 } 245 246 static int mpc85xx_serial_tstc(void) 247 { 248 volatile cbd_t *rbdf; 249 volatile scc_uart_t *up; 250 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; 251 252 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); 253 rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); 254 255 return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); 256 } 257 258 static struct serial_device mpc85xx_serial_drv = { 259 .name = "mpc85xx_serial", 260 .start = mpc85xx_serial_init, 261 .stop = NULL, 262 .setbrg = mpc85xx_serial_setbrg, 263 .putc = mpc85xx_serial_putc, 264 .puts = default_serial_puts, 265 .getc = mpc85xx_serial_getc, 266 .tstc = mpc85xx_serial_tstc, 267 }; 268 269 void mpc85xx_serial_initialize(void) 270 { 271 serial_register(&mpc85xx_serial_drv); 272 } 273 274 __weak struct serial_device *default_serial_console(void) 275 { 276 return &mpc85xx_serial_drv; 277 } 278 #endif /* CONFIG_CONS_ON_SCC */ 279