1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2003 Motorola Inc.
4  * Xianghua Xiao (X.Xiao@motorola.com)
5  * Modified based on 8260 for 8560.
6  *
7  * (C) Copyright 2000
8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9  *
10  * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
11  */
12 
13 /*
14  * Minimal serial functions needed to use one of the SCC ports
15  * as serial console interface.
16  */
17 
18 #include <common.h>
19 #include <asm/cpm_85xx.h>
20 #include <serial.h>
21 #include <linux/compiler.h>
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 #if defined(CONFIG_CONS_ON_SCC)
26 
27 #if CONFIG_CONS_INDEX == 1	/* Console on SCC1 */
28 
29 #define SCC_INDEX		0
30 #define PROFF_SCC		PROFF_SCC1
31 #define CMXSCR_MASK		(CMXSCR_GR1|CMXSCR_SC1|\
32 					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
33 #define CMXSCR_VALUE		(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
34 #define CPM_CR_SCC_PAGE		CPM_CR_SCC1_PAGE
35 #define CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK
36 
37 #elif CONFIG_CONS_INDEX == 2	/* Console on SCC2 */
38 
39 #define SCC_INDEX		1
40 #define PROFF_SCC		PROFF_SCC2
41 #define CMXSCR_MASK		(CMXSCR_GR2|CMXSCR_SC2|\
42 					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
43 #define CMXSCR_VALUE		(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
44 #define CPM_CR_SCC_PAGE		CPM_CR_SCC2_PAGE
45 #define CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK
46 
47 #elif CONFIG_CONS_INDEX == 3	/* Console on SCC3 */
48 
49 #define SCC_INDEX		2
50 #define PROFF_SCC		PROFF_SCC3
51 #define CMXSCR_MASK		(CMXSCR_GR3|CMXSCR_SC3|\
52 					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
53 #define CMXSCR_VALUE		(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
54 #define CPM_CR_SCC_PAGE		CPM_CR_SCC3_PAGE
55 #define CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK
56 
57 #elif CONFIG_CONS_INDEX == 4	/* Console on SCC4 */
58 
59 #define SCC_INDEX		3
60 #define PROFF_SCC		PROFF_SCC4
61 #define CMXSCR_MASK		(CMXSCR_GR4|CMXSCR_SC4|\
62 					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
63 #define CMXSCR_VALUE		(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
64 #define CPM_CR_SCC_PAGE		CPM_CR_SCC4_PAGE
65 #define CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK
66 
67 #else
68 
69 #error "console not correctly defined"
70 
71 #endif
72 
73 static int mpc85xx_serial_init(void)
74 {
75 	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
76 	volatile ccsr_cpm_scc_t *sp;
77 	volatile scc_uart_t *up;
78 	volatile cbd_t *tbdf, *rbdf;
79 	volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
80 	uint	dpaddr;
81 
82 	/* initialize pointers to SCC */
83 
84 	sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
85 	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
86 
87 	/* Disable transmitter/receiver.
88 	*/
89 	sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
90 
91 	/* put the SCC channel into NMSI (non multiplexd serial interface)
92 	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
93 	 */
94 	cpm->im_cpm_mux.cmxscr = \
95 		(cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
96 
97 	/* Set up the baud rate generator.
98 	*/
99 	serial_setbrg ();
100 
101 	/* Allocate space for two buffer descriptors in the DP ram.
102 	 * damm: allocating space after the two buffers for rx/tx data
103 	 */
104 
105 	dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
106 
107 	/* Set the physical address of the host memory buffers in
108 	 * the buffer descriptors.
109 	 */
110 	rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
111 	rbdf->cbd_bufaddr = (uint) (rbdf+2);
112 	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
113 	tbdf = rbdf + 1;
114 	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
115 	tbdf->cbd_sc = BD_SC_WRAP;
116 
117 	/* Set up the uart parameters in the parameter ram.
118 	*/
119 	up->scc_genscc.scc_rbase = dpaddr;
120 	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
121 	up->scc_genscc.scc_rfcr = CPMFCR_EB;
122 	up->scc_genscc.scc_tfcr = CPMFCR_EB;
123 	up->scc_genscc.scc_mrblr = 1;
124 	up->scc_maxidl = 0;
125 	up->scc_brkcr = 1;
126 	up->scc_parec = 0;
127 	up->scc_frmec = 0;
128 	up->scc_nosec = 0;
129 	up->scc_brkec = 0;
130 	up->scc_uaddr1 = 0;
131 	up->scc_uaddr2 = 0;
132 	up->scc_toseq = 0;
133 	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
134 	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
135 	up->scc_rccm = 0xc0ff;
136 
137 	/* Mask all interrupts and remove anything pending.
138 	*/
139 	sp->sccm = 0;
140 	sp->scce = 0xffff;
141 
142 	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
143 	*/
144 	sp->gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
145 	sp->gsmrl = \
146 		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
147 
148 	/* Set CTS no flow control, 1 stop bit, 8 bit character length,
149 	 * normal async UART mode, no parity
150 	 */
151 	sp->psmr = SCU_PSMR_CL;
152 
153 	/* execute the "Init Rx and Tx params" CP command.
154 	*/
155 
156 	while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
157 	  ;
158 
159 	cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
160 					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
161 
162 	while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
163 	  ;
164 
165 	/* Enable transmitter/receiver.
166 	*/
167 	sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
168 
169 	return (0);
170 }
171 
172 static void mpc85xx_serial_setbrg(void)
173 {
174 #if defined(CONFIG_CONS_USE_EXTC)
175 	m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
176 		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
177 #else
178 	m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
179 #endif
180 }
181 
182 static void mpc85xx_serial_putc(const char c)
183 {
184 	volatile scc_uart_t	*up;
185 	volatile cbd_t		*tbdf;
186 	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
187 
188 	if (c == '\n')
189 		serial_putc ('\r');
190 
191 	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
192 	tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
193 
194 	/* Wait for last character to go.
195 	 */
196 	while (tbdf->cbd_sc & BD_SC_READY)
197 		;
198 
199 	/* Load the character into the transmit buffer.
200 	 */
201 	*(volatile char *)tbdf->cbd_bufaddr = c;
202 	tbdf->cbd_datlen = 1;
203 	tbdf->cbd_sc |= BD_SC_READY;
204 }
205 
206 static int mpc85xx_serial_getc(void)
207 {
208 	volatile cbd_t		*rbdf;
209 	volatile scc_uart_t	*up;
210 	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
211 	unsigned char		c;
212 
213 	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
214 	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
215 
216 	/* Wait for character to show up.
217 	 */
218 	while (rbdf->cbd_sc & BD_SC_EMPTY)
219 		;
220 
221 	/* Grab the char and clear the buffer again.
222 	 */
223 	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
224 	rbdf->cbd_sc |= BD_SC_EMPTY;
225 
226 	return (c);
227 }
228 
229 static int mpc85xx_serial_tstc(void)
230 {
231 	volatile cbd_t		*rbdf;
232 	volatile scc_uart_t	*up;
233 	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
234 
235 	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
236 	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
237 
238 	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
239 }
240 
241 static struct serial_device mpc85xx_serial_drv = {
242 	.name	= "mpc85xx_serial",
243 	.start	= mpc85xx_serial_init,
244 	.stop	= NULL,
245 	.setbrg	= mpc85xx_serial_setbrg,
246 	.putc	= mpc85xx_serial_putc,
247 	.puts	= default_serial_puts,
248 	.getc	= mpc85xx_serial_getc,
249 	.tstc	= mpc85xx_serial_tstc,
250 };
251 
252 void mpc85xx_serial_initialize(void)
253 {
254 	serial_register(&mpc85xx_serial_drv);
255 }
256 
257 __weak struct serial_device *default_serial_console(void)
258 {
259 	return &mpc85xx_serial_drv;
260 }
261 #endif	/* CONFIG_CONS_ON_SCC */
262