1/*
2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * SPDX-License-Identifier:	GPL-2.0+
6 */
7
8#include <asm-offsets.h>
9#include <config.h>
10#include <mpc85xx.h>
11
12#include <ppc_asm.tmpl>
13#include <ppc_defs.h>
14
15#include <asm/cache.h>
16#include <asm/mmu.h>
17
18/* To boot secondary cpus, we need a place for them to start up.
19 * Normally, they start at 0xfffffffc, but that's usually the
20 * firmware, and we don't want to have to run the firmware again.
21 * Instead, the primary cpu will set the BPTR to point here to
22 * this page.  We then set up the core, and head to
23 * start_secondary.  Note that this means that the code below
24 * must never exceed 1023 instructions (the branch at the end
25 * would then be the 1024th).
26 */
27	.globl	__secondary_start_page
28	.align	12
29__secondary_start_page:
30/* First do some preliminary setup */
31	lis	r3, HID0_EMCP@h		/* enable machine check */
32#ifndef CONFIG_E500MC
33	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
34#endif
35#ifdef CONFIG_PHYS_64BIT
36	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
37#endif
38	mtspr	SPRN_HID0,r3
39
40#ifndef CONFIG_E500MC
41	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
42	mfspr   r0,PVR
43	andi.	r0,r0,0xff
44	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
45	blt 1f
46	/* Set MBDD bit also */
47	ori r3, r3, HID1_MBDD@l
481:
49	mtspr	SPRN_HID1,r3
50#endif
51
52#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
53	mfspr	r3,SPRN_HDBCR1
54	oris	r3,r3,0x0100
55	mtspr	SPRN_HDBCR1,r3
56#endif
57
58#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
59	mfspr	r3,SPRN_SVR
60	rlwinm	r3,r3,0,0xff
61	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
62	cmpw	r3,r4
63	beq	1f
64
65#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
66	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
67	cmpw	r3,r4
68	beq	1f
69#endif
70
71	/* Not a supported revision affected by erratum */
72	b	2f
73
741:	/* Erratum says set bits 55:60 to 001001 */
75	msync
76	isync
77	mfspr	r3,SPRN_HDBCR0
78	li	r4,0x48
79	rlwimi	r3,r4,0,0x1f8
80	mtspr	SPRN_HDBCR0,r3
81	isync
822:
83#endif
84
85	/* Enable branch prediction */
86	lis	r3,BUCSR_ENABLE@h
87	ori	r3,r3,BUCSR_ENABLE@l
88	mtspr	SPRN_BUCSR,r3
89
90	/* Ensure TB is 0 */
91	li	r3,0
92	mttbl	r3
93	mttbu	r3
94
95	/* Enable/invalidate the I-Cache */
96	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
97	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
98	mtspr	SPRN_L1CSR1,r2
991:
100	mfspr	r3,SPRN_L1CSR1
101	and.	r1,r3,r2
102	bne	1b
103
104	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
105	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
106	mtspr	SPRN_L1CSR1,r3
107	isync
1082:
109	mfspr	r3,SPRN_L1CSR1
110	andi.	r1,r3,L1CSR1_ICE@l
111	beq	2b
112
113	/* Enable/invalidate the D-Cache */
114	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
115	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
116	mtspr	SPRN_L1CSR0,r2
1171:
118	mfspr	r3,SPRN_L1CSR0
119	and.	r1,r3,r2
120	bne	1b
121
122	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
123	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
124	mtspr	SPRN_L1CSR0,r3
125	isync
1262:
127	mfspr	r3,SPRN_L1CSR0
128	andi.	r1,r3,L1CSR0_DCE@l
129	beq	2b
130
131#define toreset(x) (x - __secondary_start_page + 0xfffff000)
132
133	/* get our PIR to figure out our table entry */
134	lis	r3,toreset(__spin_table_addr)@h
135	ori	r3,r3,toreset(__spin_table_addr)@l
136	lwz	r3,0(r3)
137
138	mfspr	r0,SPRN_PIR
139#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
140/*
141 * PIR definition for Chassis 2
142 * 0-17 Reserved (logic 0s)
143 * 18-19 CHIP_ID,    2'b00      - SoC 1
144 *                  all others - reserved
145 * 20-24 CLUSTER_ID 5'b00000   - CCM 1
146 *                  all others - reserved
147 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
148 *                       2'b01 - cluster 2
149 *                       2'b10 - cluster 3
150 *                       2'b11 - cluster 4
151 * 27-28 CORE_ID         2'b00 - core 0
152 *                       2'b01 - core 1
153 *                       2'b10 - core 2
154 *                       2'b11 - core 3
155 * 29-31 THREAD_ID       3'b000 - thread 0
156 *                       3'b001 - thread 1
157 *
158 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
159 * and clusters by 0x20.
160 *
161 * We renumber PIR so that all threads in the system are consecutive.
162 */
163
164	rlwinm	r8,r0,29,0x03	/* r8 = core within cluster */
165	srwi	r10,r0,5	/* r10 = cluster */
166
167	mulli	r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
168	add	r5,r5,r8	/* for spin table index */
169	mulli	r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE	/* for PIR */
170#elif	defined(CONFIG_E500MC)
171	rlwinm	r4,r0,27,27,31
172	mr	r5,r4
173#else
174	mr	r4,r0
175	mr	r5,r4
176#endif
177
178	/*
179	 * r10 has the base address for the entry.
180	 * we cannot access it yet before setting up a new TLB
181	 */
182	slwi	r8,r5,6	/* spin table is padded to 64 byte */
183	add	r10,r3,r8
184
185	mtspr	SPRN_PIR,r4	/* write to PIR register */
186
187#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
188	mfspr	r8, L1CSR2
189	clrrwi	r8, r8, 10	/* clear bit [54-63] DCSTASHID */
190	mtspr	L1CSR2, r8
191#else
192#ifdef CONFIG_SYS_CACHE_STASHING
193	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
194	slwi	r8,r4,1
195	addi	r8,r8,32
196	mtspr	L1CSR2,r8
197#endif
198#endif	/* CONFIG_SYS_FSL_ERRATUM_A007907 */
199
200#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
201	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
202	/*
203	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
204	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
205	 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
206	 */
207	mfspr   r3,SPRN_SVR
208	rlwinm	r6,r3,24,~0x800		/* clear E bit */
209
210	lis	r5,SVR_P4080@h
211	ori	r5,r5,SVR_P4080@l
212	cmpw	r6,r5
213	bne	1f
214
215	rlwinm  r3,r3,0,0xf0
216	li      r5,0x30
217	cmpw    r3,r5
218	bge     2f
2191:
220#ifdef	CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
221	lis	r3,toreset(enable_cpu_a011_workaround)@ha
222	lwz	r3,toreset(enable_cpu_a011_workaround)@l(r3)
223	cmpwi	r3,0
224	beq	2f
225#endif
226	mfspr	r3,L1CSR2
227	oris	r3,r3,(L1CSR2_DCWS)@h
228	mtspr	L1CSR2,r3
2292:
230#endif
231
232#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
233	/*
234	 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
235	 * write shadow mode. This code should run after other code setting
236	 * DCWS.
237	 */
238	mfspr	r3,L1CSR2
239	andis.	r3,r3,(L1CSR2_DCWS)@h
240	beq	1f
241	mfspr	r3, SPRN_HDBCR0
242	oris	r3, r3, 0x8000
243	mtspr	SPRN_HDBCR0, r3
2441:
245#endif
246
247#ifdef CONFIG_BACKSIDE_L2_CACHE
248	/* skip L2 setup on P2040/P2040E as they have no L2 */
249	mfspr	r3,SPRN_SVR
250	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */
251
252	lis	r3,SVR_P2040@h
253	ori	r3,r3,SVR_P2040@l
254	cmpw	r6,r3
255	beq 3f
256
257	/* Enable/invalidate the L2 cache */
258	msync
259	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
260	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
261	mtspr	SPRN_L2CSR0,r2
2621:
263	mfspr	r3,SPRN_L2CSR0
264	and.	r1,r3,r2
265	bne	1b
266
267#ifdef CONFIG_SYS_CACHE_STASHING
268	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
269	addi	r3,r8,1
270	mtspr	SPRN_L2CSR1,r3
271#endif
272
273	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
274	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
275	mtspr	SPRN_L2CSR0,r3
276	isync
2772:
278	mfspr	r3,SPRN_L2CSR0
279	andis.	r1,r3,L2CSR0_L2E@h
280	beq	2b
281#endif
2823:
283	/* setup mapping for the spin table, WIMGE=0b00100 */
284	lis	r13,toreset(__spin_table_addr)@h
285	ori	r13,r13,toreset(__spin_table_addr)@l
286	lwz	r13,0(r13)
287	/* mask by 4K */
288	rlwinm	r13,r13,0,0,19
289
290	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
291	mtspr	SPRN_MAS0,r11
292	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
293	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
294	mtspr	SPRN_MAS1,r11
295	oris	r11,r13,(MAS2_M|MAS2_G)@h
296	ori	r11,r13,(MAS2_M|MAS2_G)@l
297	mtspr	SPRN_MAS2,r11
298	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
299	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
300	mtspr	SPRN_MAS3,r11
301	li	r11,0
302	mtspr	SPRN_MAS7,r11
303	tlbwe
304
305	/*
306	 * __bootpg_addr has the address of __second_half_boot_page
307	 * jump there in AS=1 space with cache enabled
308	 */
309	lis	r13,toreset(__bootpg_addr)@h
310	ori	r13,r13,toreset(__bootpg_addr)@l
311	lwz	r11,0(r13)
312	mtspr	SPRN_SRR0,r11
313	mfmsr	r13
314	ori	r12,r13,MSR_IS|MSR_DS@l
315	mtspr	SPRN_SRR1,r12
316	rfi
317
318	/*
319	 * Allocate some space for the SDRAM address of the bootpg.
320	 * This variable has to be in the boot page so that it can
321	 * be accessed by secondary cores when they come out of reset.
322	 */
323	.align L1_CACHE_SHIFT
324	.globl __bootpg_addr
325__bootpg_addr:
326	.long	0
327
328	.global __spin_table_addr
329__spin_table_addr:
330	.long	0
331
332	/*
333	 * This variable is set by cpu_init_r() after parsing hwconfig
334	 * to enable workaround for erratum NMG_CPU_A011.
335	 */
336	.align L1_CACHE_SHIFT
337	.global enable_cpu_a011_workaround
338enable_cpu_a011_workaround:
339	.long	1
340
341	/* Fill in the empty space.  The actual reset vector is
342	 * the last word of the page */
343__secondary_start_code_end:
344	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
345__secondary_reset_vector:
346	b	__secondary_start_page
347
348
349/* this is a separated page for the spin table and cacheable boot code */
350	.align L1_CACHE_SHIFT
351	.global __second_half_boot_page
352__second_half_boot_page:
353#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
354	lis	r3,(spin_table_compat - __second_half_boot_page)@h
355	ori	r3,r3,(spin_table_compat - __second_half_boot_page)@l
356	add	r3,r3,r11 /* r11 has the address of __second_half_boot_page */
357	lwz	r14,0(r3)
358#endif
359
360#define ENTRY_ADDR_UPPER	0
361#define ENTRY_ADDR_LOWER	4
362#define ENTRY_R3_UPPER		8
363#define ENTRY_R3_LOWER		12
364#define ENTRY_RESV		16
365#define ENTRY_PIR		20
366#define ENTRY_SIZE		64
367	/*
368	 * setup the entry
369	 * r10 has the base address of the spin table.
370	 * spin table is defined as
371	 * struct {
372	 *	uint64_t entry_addr;
373	 *	uint64_t r3;
374	 *	uint32_t rsvd1;
375	 *	uint32_t pir;
376	 * };
377	 * we pad this struct to 64 bytes so each entry is in its own cacheline
378	 */
379	li	r3,0
380	li	r8,1
381	mfspr	r4,SPRN_PIR
382	stw	r3,ENTRY_ADDR_UPPER(r10)
383	stw	r3,ENTRY_R3_UPPER(r10)
384	stw	r4,ENTRY_R3_LOWER(r10)
385	stw	r3,ENTRY_RESV(r10)
386	stw	r4,ENTRY_PIR(r10)
387	msync
388	stw	r8,ENTRY_ADDR_LOWER(r10)
389
390	/* spin waiting for addr */
3913:
392/*
393 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
394 * memory. Old OS may not work with this change. A patch is waiting to be
395 * accepted for Linux kernel. Other OS needs similar fix to spin table.
396 * For OSes with old spin table code, we can enable this temporary fix by
397 * setting environmental variable "spin_table_compat". For new OSes, set
398 * "spin_table_compat=no". After Linux is fixed, we can remove this macro
399 * and related code. For now, it is enabled by default.
400 */
401#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
402	cmpwi   r14,0
403	beq     4f
404	dcbf    0, r10
405	sync
4064:
407#endif
408	lwz	r4,ENTRY_ADDR_LOWER(r10)
409	andi.	r11,r4,1
410	bne	3b
411	isync
412
413	/* get the upper bits of the addr */
414	lwz	r11,ENTRY_ADDR_UPPER(r10)
415
416	/* setup branch addr */
417	mtspr	SPRN_SRR0,r4
418
419	/* mark the entry as released */
420	li	r8,3
421	stw	r8,ENTRY_ADDR_LOWER(r10)
422
423	/* mask by ~64M to setup our tlb we will jump to */
424	rlwinm	r12,r4,0,0,5
425
426	/*
427	 * setup r3, r4, r5, r6, r7, r8, r9
428	 * r3 contains the value to put in the r3 register at secondary cpu
429	 * entry. The high 32-bits are ignored on 32-bit chip implementations.
430	 * 64-bit chip implementations however shall load all 64-bits
431	 */
432#ifdef CONFIG_SYS_PPC64
433	ld	r3,ENTRY_R3_UPPER(r10)
434#else
435	lwz	r3,ENTRY_R3_LOWER(r10)
436#endif
437	li	r4,0
438	li	r5,0
439	li	r6,0
440	lis	r7,(64*1024*1024)@h
441	li	r8,0
442	li	r9,0
443
444	/* load up the pir */
445	lwz	r0,ENTRY_PIR(r10)
446	mtspr	SPRN_PIR,r0
447	mfspr	r0,SPRN_PIR
448	stw	r0,ENTRY_PIR(r10)
449
450	mtspr	IVPR,r12
451/*
452 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
453 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
454 * second mapping that maps addr 1:1 for 64M, and then we jump to
455 * addr
456 */
457	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
458	mtspr	SPRN_MAS0,r10
459	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
460	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
461	mtspr	SPRN_MAS1,r10
462	/* WIMGE = 0b00000 for now */
463	mtspr	SPRN_MAS2,r12
464	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
465	mtspr	SPRN_MAS3,r12
466#ifdef CONFIG_ENABLE_36BIT_PHYS
467	mtspr	SPRN_MAS7,r11
468#endif
469	tlbwe
470
471/* Now we have another mapping for this page, so we jump to that
472 * mapping
473 */
474	mtspr	SPRN_SRR1,r13
475	rfi
476
477
478	.align 6
479	.globl __spin_table
480__spin_table:
481	.space CONFIG_MAX_CPUS*ENTRY_SIZE
482
483#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
484	.align L1_CACHE_SHIFT
485	.global spin_table_compat
486spin_table_compat:
487	.long	1
488
489#endif
490
491__spin_table_end:
492	.space 4096 - (__spin_table_end - __spin_table)
493