1/*
2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc85xx.h>
27#include <version.h>
28
29#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36
37/* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page.  We then set up the core, and head to
42 * start_secondary.  Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
45 */
46	.globl	__secondary_start_page
47	.align	12
48__secondary_start_page:
49/* First do some preliminary setup */
50	lis	r3, HID0_EMCP@h		/* enable machine check */
51#ifndef CONFIG_E500MC
52	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
53#endif
54#ifdef CONFIG_PHYS_64BIT
55	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
56#endif
57	mtspr	SPRN_HID0,r3
58
59#ifndef CONFIG_E500MC
60	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
61	mfspr   r0,PVR
62	andi.	r0,r0,0xff
63	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
64	blt 1f
65	/* Set MBDD bit also */
66	ori r3, r3, HID1_MBDD@l
671:
68	mtspr	SPRN_HID1,r3
69#endif
70
71#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
72	mfspr	r3,977
73	oris	r3,r3,0x0100
74	mtspr	977,r3
75#endif
76
77	/* Enable branch prediction */
78	lis	r3,BUCSR_ENABLE@h
79	ori	r3,r3,BUCSR_ENABLE@l
80	mtspr	SPRN_BUCSR,r3
81
82	/* Ensure TB is 0 */
83	li	r3,0
84	mttbl	r3
85	mttbu	r3
86
87	/* Enable/invalidate the I-Cache */
88	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
89	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
90	mtspr	SPRN_L1CSR1,r2
911:
92	mfspr	r3,SPRN_L1CSR1
93	and.	r1,r3,r2
94	bne	1b
95
96	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
97	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
98	mtspr	SPRN_L1CSR1,r3
99	isync
1002:
101	mfspr	r3,SPRN_L1CSR1
102	andi.	r1,r3,L1CSR1_ICE@l
103	beq	2b
104
105	/* Enable/invalidate the D-Cache */
106	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
107	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
108	mtspr	SPRN_L1CSR0,r2
1091:
110	mfspr	r3,SPRN_L1CSR0
111	and.	r1,r3,r2
112	bne	1b
113
114	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
115	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
116	mtspr	SPRN_L1CSR0,r3
117	isync
1182:
119	mfspr	r3,SPRN_L1CSR0
120	andi.	r1,r3,L1CSR0_DCE@l
121	beq	2b
122
123#define toreset(x) (x - __secondary_start_page + 0xfffff000)
124
125	/* get our PIR to figure out our table entry */
126	lis	r3,toreset(__spin_table)@h
127	ori	r3,r3,toreset(__spin_table)@l
128
129	/* r10 has the base address for the entry */
130	mfspr	r0,SPRN_PIR
131#ifdef CONFIG_E500MC
132	rlwinm	r4,r0,27,27,31
133#else
134	mr	r4,r0
135#endif
136	slwi	r8,r4,5
137	add	r10,r3,r8
138
139#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
140	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
141	slwi	r8,r4,1
142	addi	r8,r8,32
143	mtspr	L1CSR2,r8
144#endif
145
146#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
147	mfspr	r8,L1CSR2
148	oris	r8,r8,(L1CSR2_DCWS)@h
149	mtspr	L1CSR2,r8
150#endif
151
152#ifdef CONFIG_BACKSIDE_L2_CACHE
153	/* skip L2 setup on P2040/P2040E as they have no L2 */
154	mfspr	r2,SPRN_SVR
155	lis	r3,SVR_P2040@h
156	ori	r3,r3,SVR_P2040@l
157	cmpw	r2,r3
158	beq 3f
159
160	lis	r3,SVR_P2040_E@h
161	ori	r3,r3,SVR_P2040_E@l
162	cmpw	r2,r3
163	beq 3f
164
165	/* Enable/invalidate the L2 cache */
166	msync
167	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
168	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
169	mtspr	SPRN_L2CSR0,r2
1701:
171	mfspr	r3,SPRN_L2CSR0
172	and.	r1,r3,r2
173	bne	1b
174
175#ifdef CONFIG_SYS_CACHE_STASHING
176	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
177	addi	r3,r8,1
178	mtspr	SPRN_L2CSR1,r3
179#endif
180
181	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
182	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
183	mtspr	SPRN_L2CSR0,r3
184	isync
1852:
186	mfspr	r3,SPRN_L2CSR0
187	andis.	r1,r3,L2CSR0_L2E@h
188	beq	2b
189#endif
1903:
191
192#define EPAPR_MAGIC		(0x45504150)
193#define ENTRY_ADDR_UPPER	0
194#define ENTRY_ADDR_LOWER	4
195#define ENTRY_R3_UPPER		8
196#define ENTRY_R3_LOWER		12
197#define ENTRY_RESV		16
198#define ENTRY_PIR		20
199#define ENTRY_R6_UPPER		24
200#define ENTRY_R6_LOWER		28
201#define ENTRY_SIZE		32
202
203	/* setup the entry */
204	li	r3,0
205	li	r8,1
206	stw	r0,ENTRY_PIR(r10)
207	stw	r3,ENTRY_ADDR_UPPER(r10)
208	stw	r8,ENTRY_ADDR_LOWER(r10)
209	stw	r3,ENTRY_R3_UPPER(r10)
210	stw	r4,ENTRY_R3_LOWER(r10)
211	stw	r3,ENTRY_R6_UPPER(r10)
212	stw	r3,ENTRY_R6_LOWER(r10)
213
214	/* load r13 with the address of the 'bootpg' in SDRAM */
215	lis	r13,toreset(__bootpg_addr)@h
216	ori	r13,r13,toreset(__bootpg_addr)@l
217	lwz	r13,0(r13)
218
219	/* setup mapping for AS = 1, and jump there */
220	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
221	mtspr	SPRN_MAS0,r11
222	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
223	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
224	mtspr	SPRN_MAS1,r11
225	oris	r11,r13,(MAS2_I|MAS2_G)@h
226	ori	r11,r13,(MAS2_I|MAS2_G)@l
227	mtspr	SPRN_MAS2,r11
228	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
229	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
230	mtspr	SPRN_MAS3,r11
231	tlbwe
232
233	bl	1f
2341:	mflr	r11
235	/*
236	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
237	 * this mask to fixup the cpu spin table and the address that we want
238	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
239	 * bootpg is at 0x7ffff000 in SDRAM.
240	 */
241	ori	r13,r13,0xfff
242	and	r11, r11, r13
243	and	r10, r10, r13
244
245	addi	r11,r11,(2f-1b)
246	mfmsr	r13
247	ori	r12,r13,MSR_IS|MSR_DS@l
248
249	mtspr	SPRN_SRR0,r11
250	mtspr	SPRN_SRR1,r12
251	rfi
252
253	/* spin waiting for addr */
2542:
255	lwz	r4,ENTRY_ADDR_LOWER(r10)
256	andi.	r11,r4,1
257	bne	2b
258	isync
259
260	/* setup IVORs to match fixed offsets */
261#include "fixed_ivor.S"
262
263	/* get the upper bits of the addr */
264	lwz	r11,ENTRY_ADDR_UPPER(r10)
265
266	/* setup branch addr */
267	mtspr	SPRN_SRR0,r4
268
269	/* mark the entry as released */
270	li	r8,3
271	stw	r8,ENTRY_ADDR_LOWER(r10)
272
273	/* mask by ~64M to setup our tlb we will jump to */
274	rlwinm	r12,r4,0,0,5
275
276	/* setup r3, r4, r5, r6, r7, r8, r9 */
277	lwz	r3,ENTRY_R3_LOWER(r10)
278	li	r4,0
279	li	r5,0
280	lwz	r6,ENTRY_R6_LOWER(r10)
281	lis	r7,(64*1024*1024)@h
282	li	r8,0
283	li	r9,0
284
285	/* load up the pir */
286	lwz	r0,ENTRY_PIR(r10)
287	mtspr	SPRN_PIR,r0
288	mfspr	r0,SPRN_PIR
289	stw	r0,ENTRY_PIR(r10)
290
291	mtspr	IVPR,r12
292/*
293 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
294 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
295 * second mapping that maps addr 1:1 for 64M, and then we jump to
296 * addr
297 */
298	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
299	mtspr	SPRN_MAS0,r10
300	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
301	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
302	mtspr	SPRN_MAS1,r10
303	/* WIMGE = 0b00000 for now */
304	mtspr	SPRN_MAS2,r12
305	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
306	mtspr	SPRN_MAS3,r12
307#ifdef CONFIG_ENABLE_36BIT_PHYS
308	mtspr	SPRN_MAS7,r11
309#endif
310	tlbwe
311
312/* Now we have another mapping for this page, so we jump to that
313 * mapping
314 */
315	mtspr	SPRN_SRR1,r13
316	rfi
317
318	/*
319	 * Allocate some space for the SDRAM address of the bootpg.
320	 * This variable has to be in the boot page so that it can
321	 * be accessed by secondary cores when they come out of reset.
322	 */
323	.globl __bootpg_addr
324__bootpg_addr:
325	.long	0
326
327	.align L1_CACHE_SHIFT
328	.globl __spin_table
329__spin_table:
330	.space CONFIG_MAX_CPUS*ENTRY_SIZE
331
332	/* Fill in the empty space.  The actual reset vector is
333	 * the last word of the page */
334__secondary_start_code_end:
335	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
336__secondary_reset_vector:
337	b	__secondary_start_page
338