1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc85xx.h>
27#include <version.h>
28
29#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36
37/* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page.  We then set up the core, and head to
42 * start_secondary.  Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
45 */
46	.globl	__secondary_start_page
47	.align	12
48__secondary_start_page:
49/* First do some preliminary setup */
50	lis	r3, HID0_EMCP@h		/* enable machine check */
51#ifndef CONFIG_E500MC
52	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
53#endif
54#ifdef CONFIG_PHYS_64BIT
55	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
56#endif
57	mtspr	SPRN_HID0,r3
58
59#ifndef CONFIG_E500MC
60	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
61	mfspr   r0,PVR
62	andi.	r0,r0,0xff
63	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
64	blt 1f
65	/* Set MBDD bit also */
66	ori r3, r3, HID1_MBDD@l
671:
68	mtspr	SPRN_HID1,r3
69#endif
70
71	/* Enable branch prediction */
72	lis	r3,BUCSR_ENABLE@h
73	ori	r3,r3,BUCSR_ENABLE@l
74	mtspr	SPRN_BUCSR,r3
75
76	/* Ensure TB is 0 */
77	li	r3,0
78	mttbl	r3
79	mttbu	r3
80
81	/* Enable/invalidate the I-Cache */
82	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
83	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
84	mtspr	SPRN_L1CSR1,r2
851:
86	mfspr	r3,SPRN_L1CSR1
87	and.	r1,r3,r2
88	bne	1b
89
90	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
91	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
92	mtspr	SPRN_L1CSR1,r3
93	isync
942:
95	mfspr	r3,SPRN_L1CSR1
96	andi.	r1,r3,L1CSR1_ICE@l
97	beq	2b
98
99	/* Enable/invalidate the D-Cache */
100	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
101	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
102	mtspr	SPRN_L1CSR0,r2
1031:
104	mfspr	r3,SPRN_L1CSR0
105	and.	r1,r3,r2
106	bne	1b
107
108	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
109	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
110	mtspr	SPRN_L1CSR0,r3
111	isync
1122:
113	mfspr	r3,SPRN_L1CSR0
114	andi.	r1,r3,L1CSR0_DCE@l
115	beq	2b
116
117#define toreset(x) (x - __secondary_start_page + 0xfffff000)
118
119	/* get our PIR to figure out our table entry */
120	lis	r3,toreset(__spin_table)@h
121	ori	r3,r3,toreset(__spin_table)@l
122
123	/* r10 has the base address for the entry */
124	mfspr	r0,SPRN_PIR
125#ifdef CONFIG_E500MC
126	rlwinm	r4,r0,27,27,31
127#else
128	mr	r4,r0
129#endif
130	slwi	r8,r4,5
131	add	r10,r3,r8
132
133#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
134	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
135	slwi	r8,r4,1
136	addi	r8,r8,32
137	mtspr	L1CSR2,r8
138#endif
139
140#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
141	mfspr	r8,L1CSR2
142	oris	r8,r8,(L1CSR2_DCWS)@h
143	mtspr	L1CSR2,r8
144#endif
145
146#ifdef CONFIG_BACKSIDE_L2_CACHE
147	/* Enable/invalidate the L2 cache */
148	msync
149	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
150	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
151	mtspr	SPRN_L2CSR0,r2
1521:
153	mfspr	r3,SPRN_L2CSR0
154	and.	r1,r3,r2
155	bne	1b
156
157#ifdef CONFIG_SYS_CACHE_STASHING
158	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
159	addi	r3,r8,1
160	mtspr	SPRN_L2CSR1,r3
161#endif
162
163	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
164	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
165	mtspr	SPRN_L2CSR0,r3
166	isync
1672:
168	mfspr	r3,SPRN_L2CSR0
169	andis.	r1,r3,L2CSR0_L2E@h
170	beq	2b
171#endif
172
173#define EPAPR_MAGIC		(0x45504150)
174#define ENTRY_ADDR_UPPER	0
175#define ENTRY_ADDR_LOWER	4
176#define ENTRY_R3_UPPER		8
177#define ENTRY_R3_LOWER		12
178#define ENTRY_RESV		16
179#define ENTRY_PIR		20
180#define ENTRY_R6_UPPER		24
181#define ENTRY_R6_LOWER		28
182#define ENTRY_SIZE		32
183
184	/* setup the entry */
185	li	r3,0
186	li	r8,1
187	stw	r0,ENTRY_PIR(r10)
188	stw	r3,ENTRY_ADDR_UPPER(r10)
189	stw	r8,ENTRY_ADDR_LOWER(r10)
190	stw	r3,ENTRY_R3_UPPER(r10)
191	stw	r4,ENTRY_R3_LOWER(r10)
192	stw	r3,ENTRY_R6_UPPER(r10)
193	stw	r3,ENTRY_R6_LOWER(r10)
194
195	/* load r13 with the address of the 'bootpg' in SDRAM */
196	lis	r13,toreset(__bootpg_addr)@h
197	ori	r13,r13,toreset(__bootpg_addr)@l
198	lwz	r13,0(r13)
199
200	/* setup mapping for AS = 1, and jump there */
201	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
202	mtspr	SPRN_MAS0,r11
203	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
204	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
205	mtspr	SPRN_MAS1,r11
206	oris	r11,r13,(MAS2_I|MAS2_G)@h
207	ori	r11,r13,(MAS2_I|MAS2_G)@l
208	mtspr	SPRN_MAS2,r11
209	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
210	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
211	mtspr	SPRN_MAS3,r11
212	tlbwe
213
214	bl	1f
2151:	mflr	r11
216	/*
217	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
218	 * this mask to fixup the cpu spin table and the address that we want
219	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
220	 * bootpg is at 0x7ffff000 in SDRAM.
221	 */
222	ori	r13,r13,0xfff
223	and	r11, r11, r13
224	and	r10, r10, r13
225
226	addi	r11,r11,(2f-1b)
227	mfmsr	r13
228	ori	r12,r13,MSR_IS|MSR_DS@l
229
230	mtspr	SPRN_SRR0,r11
231	mtspr	SPRN_SRR1,r12
232	rfi
233
234	/* spin waiting for addr */
2352:
236	lwz	r4,ENTRY_ADDR_LOWER(r10)
237	andi.	r11,r4,1
238	bne	2b
239	isync
240
241	/* setup IVORs to match fixed offsets */
242#include "fixed_ivor.S"
243
244	/* get the upper bits of the addr */
245	lwz	r11,ENTRY_ADDR_UPPER(r10)
246
247	/* setup branch addr */
248	mtspr	SPRN_SRR0,r4
249
250	/* mark the entry as released */
251	li	r8,3
252	stw	r8,ENTRY_ADDR_LOWER(r10)
253
254	/* mask by ~64M to setup our tlb we will jump to */
255	rlwinm	r12,r4,0,0,5
256
257	/* setup r3, r4, r5, r6, r7, r8, r9 */
258	lwz	r3,ENTRY_R3_LOWER(r10)
259	li	r4,0
260	li	r5,0
261	lwz	r6,ENTRY_R6_LOWER(r10)
262	lis	r7,(64*1024*1024)@h
263	li	r8,0
264	li	r9,0
265
266	/* load up the pir */
267	lwz	r0,ENTRY_PIR(r10)
268	mtspr	SPRN_PIR,r0
269	mfspr	r0,SPRN_PIR
270	stw	r0,ENTRY_PIR(r10)
271
272	mtspr	IVPR,r12
273/*
274 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
275 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
276 * second mapping that maps addr 1:1 for 64M, and then we jump to
277 * addr
278 */
279	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
280	mtspr	SPRN_MAS0,r10
281	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
282	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
283	mtspr	SPRN_MAS1,r10
284	/* WIMGE = 0b00000 for now */
285	mtspr	SPRN_MAS2,r12
286	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
287	mtspr	SPRN_MAS3,r12
288#ifdef CONFIG_ENABLE_36BIT_PHYS
289	mtspr	SPRN_MAS7,r11
290#endif
291	tlbwe
292
293/* Now we have another mapping for this page, so we jump to that
294 * mapping
295 */
296	mtspr	SPRN_SRR1,r13
297	rfi
298
299	/*
300	 * Allocate some space for the SDRAM address of the bootpg.
301	 * This variable has to be in the boot page so that it can
302	 * be accessed by secondary cores when they come out of reset.
303	 */
304	.globl __bootpg_addr
305__bootpg_addr:
306	.long	0
307
308	.align L1_CACHE_SHIFT
309	.globl __spin_table
310__spin_table:
311	.space CONFIG_MAX_CPUS*ENTRY_SIZE
312
313	/* Fill in the empty space.  The actual reset vector is
314	 * the last word of the page */
315__secondary_start_code_end:
316	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
317__secondary_reset_vector:
318	b	__secondary_start_page
319