1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include <mpc85xx.h>
26#include <version.h>
27
28#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
29
30#include <ppc_asm.tmpl>
31#include <ppc_defs.h>
32
33#include <asm/cache.h>
34#include <asm/mmu.h>
35
36/* To boot secondary cpus, we need a place for them to start up.
37 * Normally, they start at 0xfffffffc, but that's usually the
38 * firmware, and we don't want to have to run the firmware again.
39 * Instead, the primary cpu will set the BPTR to point here to
40 * this page.  We then set up the core, and head to
41 * start_secondary.  Note that this means that the code below
42 * must never exceed 1023 instructions (the branch at the end
43 * would then be the 1024th).
44 */
45	.globl	__secondary_start_page
46	.align	12
47__secondary_start_page:
48/* First do some preliminary setup */
49	lis	r3, HID0_EMCP@h		/* enable machine check */
50#ifndef CONFIG_E500MC
51	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
52#endif
53#ifdef CONFIG_PHYS_64BIT
54	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
55#endif
56	mtspr	SPRN_HID0,r3
57
58#ifndef CONFIG_E500MC
59	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
60	mfspr   r0,PVR
61	andi.	r0,r0,0xff
62	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
63	blt 1f
64	/* Set MBDD bit also */
65	ori r3, r3, HID1_MBDD@l
661:
67	mtspr	SPRN_HID1,r3
68#endif
69
70	/* Enable branch prediction */
71	lis	r3,BUCSR_ENABLE@h
72	ori	r3,r3,BUCSR_ENABLE@l
73	mtspr	SPRN_BUCSR,r3
74
75	/* Ensure TB is 0 */
76	li	r3,0
77	mttbl	r3
78	mttbu	r3
79
80	/* Enable/invalidate the I-Cache */
81	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
82	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
83	mtspr	SPRN_L1CSR1,r2
841:
85	mfspr	r3,SPRN_L1CSR1
86	and.	r1,r3,r2
87	bne	1b
88
89	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
90	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
91	mtspr	SPRN_L1CSR1,r3
92	isync
932:
94	mfspr	r3,SPRN_L1CSR1
95	andi.	r1,r3,L1CSR1_ICE@l
96	beq	2b
97
98	/* Enable/invalidate the D-Cache */
99	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
100	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
101	mtspr	SPRN_L1CSR0,r2
1021:
103	mfspr	r3,SPRN_L1CSR0
104	and.	r1,r3,r2
105	bne	1b
106
107	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
108	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
109	mtspr	SPRN_L1CSR0,r3
110	isync
1112:
112	mfspr	r3,SPRN_L1CSR0
113	andi.	r1,r3,L1CSR0_DCE@l
114	beq	2b
115
116#define toreset(x) (x - __secondary_start_page + 0xfffff000)
117
118	/* get our PIR to figure out our table entry */
119	lis	r3,toreset(__spin_table)@h
120	ori	r3,r3,toreset(__spin_table)@l
121
122	/* r10 has the base address for the entry */
123	mfspr	r0,SPRN_PIR
124#ifdef CONFIG_E500MC
125	rlwinm	r4,r0,27,27,31
126#else
127	mr	r4,r0
128#endif
129	slwi	r8,r4,5
130	add	r10,r3,r8
131
132#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
133	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
134	slwi	r8,r4,1
135	addi	r8,r8,32
136	mtspr	L1CSR2,r8
137#endif
138
139#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
140	mfspr	r8,L1CSR2
141	oris	r8,r8,(L1CSR2_DCWS)@h
142	mtspr	L1CSR2,r8
143#endif
144
145#ifdef CONFIG_BACKSIDE_L2_CACHE
146	/* Enable/invalidate the L2 cache */
147	msync
148	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
149	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
150	mtspr	SPRN_L2CSR0,r2
1511:
152	mfspr	r3,SPRN_L2CSR0
153	and.	r1,r3,r2
154	bne	1b
155
156#ifdef CONFIG_SYS_CACHE_STASHING
157	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
158	addi	r3,r8,1
159	mtspr	SPRN_L2CSR1,r3
160#endif
161
162	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
163	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
164	mtspr	SPRN_L2CSR0,r3
165	isync
1662:
167	mfspr	r3,SPRN_L2CSR0
168	andis.	r1,r3,L2CSR0_L2E@h
169	beq	2b
170#endif
171
172#define EPAPR_MAGIC		(0x45504150)
173#define ENTRY_ADDR_UPPER	0
174#define ENTRY_ADDR_LOWER	4
175#define ENTRY_R3_UPPER		8
176#define ENTRY_R3_LOWER		12
177#define ENTRY_RESV		16
178#define ENTRY_PIR		20
179#define ENTRY_R6_UPPER		24
180#define ENTRY_R6_LOWER		28
181#define ENTRY_SIZE		32
182
183	/* setup the entry */
184	li	r3,0
185	li	r8,1
186	stw	r0,ENTRY_PIR(r10)
187	stw	r3,ENTRY_ADDR_UPPER(r10)
188	stw	r8,ENTRY_ADDR_LOWER(r10)
189	stw	r3,ENTRY_R3_UPPER(r10)
190	stw	r4,ENTRY_R3_LOWER(r10)
191	stw	r3,ENTRY_R6_UPPER(r10)
192	stw	r3,ENTRY_R6_LOWER(r10)
193
194	/* load r13 with the address of the 'bootpg' in SDRAM */
195	lis	r13,toreset(__bootpg_addr)@h
196	ori	r13,r13,toreset(__bootpg_addr)@l
197	lwz	r13,0(r13)
198
199	/* setup mapping for AS = 1, and jump there */
200	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
201	mtspr	SPRN_MAS0,r11
202	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
203	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
204	mtspr	SPRN_MAS1,r11
205	oris	r11,r13,(MAS2_I|MAS2_G)@h
206	ori	r11,r13,(MAS2_I|MAS2_G)@l
207	mtspr	SPRN_MAS2,r11
208	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
209	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
210	mtspr	SPRN_MAS3,r11
211	tlbwe
212
213	bl	1f
2141:	mflr	r11
215	/*
216	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
217	 * this mask to fixup the cpu spin table and the address that we want
218	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
219	 * bootpg is at 0x7ffff000 in SDRAM.
220	 */
221	ori	r13,r13,0xfff
222	and	r11, r11, r13
223	and	r10, r10, r13
224
225	addi	r11,r11,(2f-1b)
226	mfmsr	r13
227	ori	r12,r13,MSR_IS|MSR_DS@l
228
229	mtspr	SPRN_SRR0,r11
230	mtspr	SPRN_SRR1,r12
231	rfi
232
233	/* spin waiting for addr */
2342:
235	lwz	r4,ENTRY_ADDR_LOWER(r10)
236	andi.	r11,r4,1
237	bne	2b
238	isync
239
240	/* setup IVORs to match fixed offsets */
241#include "fixed_ivor.S"
242
243	/* get the upper bits of the addr */
244	lwz	r11,ENTRY_ADDR_UPPER(r10)
245
246	/* setup branch addr */
247	mtspr	SPRN_SRR0,r4
248
249	/* mark the entry as released */
250	li	r8,3
251	stw	r8,ENTRY_ADDR_LOWER(r10)
252
253	/* mask by ~64M to setup our tlb we will jump to */
254	rlwinm	r12,r4,0,0,5
255
256	/* setup r3, r4, r5, r6, r7, r8, r9 */
257	lwz	r3,ENTRY_R3_LOWER(r10)
258	li	r4,0
259	li	r5,0
260	lwz	r6,ENTRY_R6_LOWER(r10)
261	lis	r7,(64*1024*1024)@h
262	li	r8,0
263	li	r9,0
264
265	/* load up the pir */
266	lwz	r0,ENTRY_PIR(r10)
267	mtspr	SPRN_PIR,r0
268	mfspr	r0,SPRN_PIR
269	stw	r0,ENTRY_PIR(r10)
270
271	mtspr	IVPR,r12
272/*
273 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
274 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
275 * second mapping that maps addr 1:1 for 64M, and then we jump to
276 * addr
277 */
278	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
279	mtspr	SPRN_MAS0,r10
280	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
281	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
282	mtspr	SPRN_MAS1,r10
283	/* WIMGE = 0b00000 for now */
284	mtspr	SPRN_MAS2,r12
285	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
286	mtspr	SPRN_MAS3,r12
287#ifdef CONFIG_ENABLE_36BIT_PHYS
288	mtspr	SPRN_MAS7,r11
289#endif
290	tlbwe
291
292/* Now we have another mapping for this page, so we jump to that
293 * mapping
294 */
295	mtspr	SPRN_SRR1,r13
296	rfi
297
298	/*
299	 * Allocate some space for the SDRAM address of the bootpg.
300	 * This variable has to be in the boot page so that it can
301	 * be accessed by secondary cores when they come out of reset.
302	 */
303	.globl __bootpg_addr
304__bootpg_addr:
305	.long	0
306
307	.align L1_CACHE_SHIFT
308	.globl __spin_table
309__spin_table:
310	.space CONFIG_MAX_CPUS*ENTRY_SIZE
311
312	/* Fill in the empty space.  The actual reset vector is
313	 * the last word of the page */
314__secondary_start_code_end:
315	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
316__secondary_reset_vector:
317	b	__secondary_start_page
318