1/*
2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc85xx.h>
27#include <version.h>
28
29#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36
37/* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page.  We then set up the core, and head to
42 * start_secondary.  Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
45 */
46	.globl	__secondary_start_page
47	.align	12
48__secondary_start_page:
49/* First do some preliminary setup */
50	lis	r3, HID0_EMCP@h		/* enable machine check */
51#ifndef CONFIG_E500MC
52	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
53#endif
54#ifdef CONFIG_PHYS_64BIT
55	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
56#endif
57	mtspr	SPRN_HID0,r3
58
59#ifndef CONFIG_E500MC
60	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
61	mfspr   r0,PVR
62	andi.	r0,r0,0xff
63	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
64	blt 1f
65	/* Set MBDD bit also */
66	ori r3, r3, HID1_MBDD@l
671:
68	mtspr	SPRN_HID1,r3
69#endif
70
71	/* Enable branch prediction */
72	lis	r3,BUCSR_ENABLE@h
73	ori	r3,r3,BUCSR_ENABLE@l
74	mtspr	SPRN_BUCSR,r3
75
76	/* Ensure TB is 0 */
77	li	r3,0
78	mttbl	r3
79	mttbu	r3
80
81	/* Enable/invalidate the I-Cache */
82	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
83	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
84	mtspr	SPRN_L1CSR1,r2
851:
86	mfspr	r3,SPRN_L1CSR1
87	and.	r1,r3,r2
88	bne	1b
89
90	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
91	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
92	mtspr	SPRN_L1CSR1,r3
93	isync
942:
95	mfspr	r3,SPRN_L1CSR1
96	andi.	r1,r3,L1CSR1_ICE@l
97	beq	2b
98
99	/* Enable/invalidate the D-Cache */
100	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
101	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
102	mtspr	SPRN_L1CSR0,r2
1031:
104	mfspr	r3,SPRN_L1CSR0
105	and.	r1,r3,r2
106	bne	1b
107
108	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
109	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
110	mtspr	SPRN_L1CSR0,r3
111	isync
1122:
113	mfspr	r3,SPRN_L1CSR0
114	andi.	r1,r3,L1CSR0_DCE@l
115	beq	2b
116
117#define toreset(x) (x - __secondary_start_page + 0xfffff000)
118
119	/* get our PIR to figure out our table entry */
120	lis	r3,toreset(__spin_table)@h
121	ori	r3,r3,toreset(__spin_table)@l
122
123	/* r10 has the base address for the entry */
124	mfspr	r0,SPRN_PIR
125#ifdef CONFIG_E500MC
126	rlwinm	r4,r0,27,27,31
127#else
128	mr	r4,r0
129#endif
130	slwi	r8,r4,5
131	add	r10,r3,r8
132
133#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
134	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
135	slwi	r8,r4,1
136	addi	r8,r8,32
137	mtspr	L1CSR2,r8
138#endif
139
140#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
141	mfspr	r8,L1CSR2
142	oris	r8,r8,(L1CSR2_DCWS)@h
143	mtspr	L1CSR2,r8
144#endif
145
146#ifdef CONFIG_BACKSIDE_L2_CACHE
147	/* skip L2 setup on P2040/P2040E as they have no L2 */
148	mfspr	r2,SPRN_SVR
149	lis	r3,SVR_P2040@h
150	ori	r3,r3,SVR_P2040@l
151	cmpw	r2,r3
152	beq 3f
153
154	lis	r3,SVR_P2040_E@h
155	ori	r3,r3,SVR_P2040_E@l
156	cmpw	r2,r3
157	beq 3f
158
159	/* Enable/invalidate the L2 cache */
160	msync
161	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
162	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
163	mtspr	SPRN_L2CSR0,r2
1641:
165	mfspr	r3,SPRN_L2CSR0
166	and.	r1,r3,r2
167	bne	1b
168
169#ifdef CONFIG_SYS_CACHE_STASHING
170	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
171	addi	r3,r8,1
172	mtspr	SPRN_L2CSR1,r3
173#endif
174
175	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
176	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
177	mtspr	SPRN_L2CSR0,r3
178	isync
1792:
180	mfspr	r3,SPRN_L2CSR0
181	andis.	r1,r3,L2CSR0_L2E@h
182	beq	2b
183#endif
1843:
185
186#define EPAPR_MAGIC		(0x45504150)
187#define ENTRY_ADDR_UPPER	0
188#define ENTRY_ADDR_LOWER	4
189#define ENTRY_R3_UPPER		8
190#define ENTRY_R3_LOWER		12
191#define ENTRY_RESV		16
192#define ENTRY_PIR		20
193#define ENTRY_R6_UPPER		24
194#define ENTRY_R6_LOWER		28
195#define ENTRY_SIZE		32
196
197	/* setup the entry */
198	li	r3,0
199	li	r8,1
200	stw	r0,ENTRY_PIR(r10)
201	stw	r3,ENTRY_ADDR_UPPER(r10)
202	stw	r8,ENTRY_ADDR_LOWER(r10)
203	stw	r3,ENTRY_R3_UPPER(r10)
204	stw	r4,ENTRY_R3_LOWER(r10)
205	stw	r3,ENTRY_R6_UPPER(r10)
206	stw	r3,ENTRY_R6_LOWER(r10)
207
208	/* load r13 with the address of the 'bootpg' in SDRAM */
209	lis	r13,toreset(__bootpg_addr)@h
210	ori	r13,r13,toreset(__bootpg_addr)@l
211	lwz	r13,0(r13)
212
213	/* setup mapping for AS = 1, and jump there */
214	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
215	mtspr	SPRN_MAS0,r11
216	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
217	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
218	mtspr	SPRN_MAS1,r11
219	oris	r11,r13,(MAS2_I|MAS2_G)@h
220	ori	r11,r13,(MAS2_I|MAS2_G)@l
221	mtspr	SPRN_MAS2,r11
222	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
223	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
224	mtspr	SPRN_MAS3,r11
225	tlbwe
226
227	bl	1f
2281:	mflr	r11
229	/*
230	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
231	 * this mask to fixup the cpu spin table and the address that we want
232	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
233	 * bootpg is at 0x7ffff000 in SDRAM.
234	 */
235	ori	r13,r13,0xfff
236	and	r11, r11, r13
237	and	r10, r10, r13
238
239	addi	r11,r11,(2f-1b)
240	mfmsr	r13
241	ori	r12,r13,MSR_IS|MSR_DS@l
242
243	mtspr	SPRN_SRR0,r11
244	mtspr	SPRN_SRR1,r12
245	rfi
246
247	/* spin waiting for addr */
2482:
249	lwz	r4,ENTRY_ADDR_LOWER(r10)
250	andi.	r11,r4,1
251	bne	2b
252	isync
253
254	/* setup IVORs to match fixed offsets */
255#include "fixed_ivor.S"
256
257	/* get the upper bits of the addr */
258	lwz	r11,ENTRY_ADDR_UPPER(r10)
259
260	/* setup branch addr */
261	mtspr	SPRN_SRR0,r4
262
263	/* mark the entry as released */
264	li	r8,3
265	stw	r8,ENTRY_ADDR_LOWER(r10)
266
267	/* mask by ~64M to setup our tlb we will jump to */
268	rlwinm	r12,r4,0,0,5
269
270	/* setup r3, r4, r5, r6, r7, r8, r9 */
271	lwz	r3,ENTRY_R3_LOWER(r10)
272	li	r4,0
273	li	r5,0
274	lwz	r6,ENTRY_R6_LOWER(r10)
275	lis	r7,(64*1024*1024)@h
276	li	r8,0
277	li	r9,0
278
279	/* load up the pir */
280	lwz	r0,ENTRY_PIR(r10)
281	mtspr	SPRN_PIR,r0
282	mfspr	r0,SPRN_PIR
283	stw	r0,ENTRY_PIR(r10)
284
285	mtspr	IVPR,r12
286/*
287 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
288 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
289 * second mapping that maps addr 1:1 for 64M, and then we jump to
290 * addr
291 */
292	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
293	mtspr	SPRN_MAS0,r10
294	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
295	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
296	mtspr	SPRN_MAS1,r10
297	/* WIMGE = 0b00000 for now */
298	mtspr	SPRN_MAS2,r12
299	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
300	mtspr	SPRN_MAS3,r12
301#ifdef CONFIG_ENABLE_36BIT_PHYS
302	mtspr	SPRN_MAS7,r11
303#endif
304	tlbwe
305
306/* Now we have another mapping for this page, so we jump to that
307 * mapping
308 */
309	mtspr	SPRN_SRR1,r13
310	rfi
311
312	/*
313	 * Allocate some space for the SDRAM address of the bootpg.
314	 * This variable has to be in the boot page so that it can
315	 * be accessed by secondary cores when they come out of reset.
316	 */
317	.globl __bootpg_addr
318__bootpg_addr:
319	.long	0
320
321	.align L1_CACHE_SHIFT
322	.globl __spin_table
323__spin_table:
324	.space CONFIG_MAX_CPUS*ENTRY_SIZE
325
326	/* Fill in the empty space.  The actual reset vector is
327	 * the last word of the page */
328__secondary_start_code_end:
329	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
330__secondary_reset_vector:
331	b	__secondary_start_page
332