1/*
2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * SPDX-License-Identifier:	GPL-2.0+
6 */
7
8#include <asm-offsets.h>
9#include <config.h>
10#include <mpc85xx.h>
11#include <version.h>
12
13#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
14
15#include <ppc_asm.tmpl>
16#include <ppc_defs.h>
17
18#include <asm/cache.h>
19#include <asm/mmu.h>
20
21/* To boot secondary cpus, we need a place for them to start up.
22 * Normally, they start at 0xfffffffc, but that's usually the
23 * firmware, and we don't want to have to run the firmware again.
24 * Instead, the primary cpu will set the BPTR to point here to
25 * this page.  We then set up the core, and head to
26 * start_secondary.  Note that this means that the code below
27 * must never exceed 1023 instructions (the branch at the end
28 * would then be the 1024th).
29 */
30	.globl	__secondary_start_page
31	.align	12
32__secondary_start_page:
33/* First do some preliminary setup */
34	lis	r3, HID0_EMCP@h		/* enable machine check */
35#ifndef CONFIG_E500MC
36	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
37#endif
38#ifdef CONFIG_PHYS_64BIT
39	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
40#endif
41	mtspr	SPRN_HID0,r3
42
43#ifndef CONFIG_E500MC
44	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
45	mfspr   r0,PVR
46	andi.	r0,r0,0xff
47	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
48	blt 1f
49	/* Set MBDD bit also */
50	ori r3, r3, HID1_MBDD@l
511:
52	mtspr	SPRN_HID1,r3
53#endif
54
55#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
56	mfspr	r3,SPRN_HDBCR1
57	oris	r3,r3,0x0100
58	mtspr	SPRN_HDBCR1,r3
59#endif
60
61#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
62	mfspr	r3,SPRN_SVR
63	rlwinm	r3,r3,0,0xff
64	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
65	cmpw	r3,r4
66	beq	1f
67
68#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
69	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
70	cmpw	r3,r4
71	beq	1f
72#endif
73
74	/* Not a supported revision affected by erratum */
75	b	2f
76
771:	/* Erratum says set bits 55:60 to 001001 */
78	msync
79	isync
80	mfspr	r3,SPRN_HDBCR0
81	li	r4,0x48
82	rlwimi	r3,r4,0,0x1f8
83	mtspr	SPRN_HDBCR0,r3
84	isync
852:
86#endif
87
88	/* Enable branch prediction */
89	lis	r3,BUCSR_ENABLE@h
90	ori	r3,r3,BUCSR_ENABLE@l
91	mtspr	SPRN_BUCSR,r3
92
93	/* Ensure TB is 0 */
94	li	r3,0
95	mttbl	r3
96	mttbu	r3
97
98	/* Enable/invalidate the I-Cache */
99	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
100	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
101	mtspr	SPRN_L1CSR1,r2
1021:
103	mfspr	r3,SPRN_L1CSR1
104	and.	r1,r3,r2
105	bne	1b
106
107	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
108	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
109	mtspr	SPRN_L1CSR1,r3
110	isync
1112:
112	mfspr	r3,SPRN_L1CSR1
113	andi.	r1,r3,L1CSR1_ICE@l
114	beq	2b
115
116	/* Enable/invalidate the D-Cache */
117	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
118	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
119	mtspr	SPRN_L1CSR0,r2
1201:
121	mfspr	r3,SPRN_L1CSR0
122	and.	r1,r3,r2
123	bne	1b
124
125	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
126	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
127	mtspr	SPRN_L1CSR0,r3
128	isync
1292:
130	mfspr	r3,SPRN_L1CSR0
131	andi.	r1,r3,L1CSR0_DCE@l
132	beq	2b
133
134#define toreset(x) (x - __secondary_start_page + 0xfffff000)
135
136	/* get our PIR to figure out our table entry */
137	lis	r3,toreset(__spin_table_addr)@h
138	ori	r3,r3,toreset(__spin_table_addr)@l
139	lwz	r3,0(r3)
140
141	mfspr	r0,SPRN_PIR
142#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
143/*
144 * PIR definition for Chassis 2
145 * 0-17 Reserved (logic 0s)
146 * 18-19 CHIP_ID,    2'b00      - SoC 1
147 *                  all others - reserved
148 * 20-24 CLUSTER_ID 5'b00000   - CCM 1
149 *                  all others - reserved
150 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
151 *                       2'b01 - cluster 2
152 *                       2'b10 - cluster 3
153 *                       2'b11 - cluster 4
154 * 27-28 CORE_ID         2'b00 - core 0
155 *                       2'b01 - core 1
156 *                       2'b10 - core 2
157 *                       2'b11 - core 3
158 * 29-31 THREAD_ID       3'b000 - thread 0
159 *                       3'b001 - thread 1
160 *
161 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
162 * and clusters by 0x20.
163 *
164 * We renumber PIR so that all threads in the system are consecutive.
165 */
166
167	rlwinm	r8,r0,29,0x03	/* r8 = core within cluster */
168	srwi	r10,r0,5	/* r10 = cluster */
169
170	mulli	r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
171	add	r5,r5,r8	/* for spin table index */
172	mulli	r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE	/* for PIR */
173#elif	defined(CONFIG_E500MC)
174	rlwinm	r4,r0,27,27,31
175	mr	r5,r4
176#else
177	mr	r4,r0
178	mr	r5,r4
179#endif
180
181	/*
182	 * r10 has the base address for the entry.
183	 * we cannot access it yet before setting up a new TLB
184	 */
185	slwi	r8,r5,6	/* spin table is padded to 64 byte */
186	add	r10,r3,r8
187
188	mtspr	SPRN_PIR,r4	/* write to PIR register */
189
190#ifdef CONFIG_SYS_CACHE_STASHING
191	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
192	slwi	r8,r4,1
193	addi	r8,r8,32
194	mtspr	L1CSR2,r8
195#endif
196
197#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
198	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
199	/*
200	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
201	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
202	 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
203	 */
204	mfspr   r3,SPRN_SVR
205	rlwinm	r6,r3,24,~0x800		/* clear E bit */
206
207	lis	r5,SVR_P4080@h
208	ori	r5,r5,SVR_P4080@l
209	cmpw	r6,r5
210	bne	1f
211
212	rlwinm  r3,r3,0,0xf0
213	li      r5,0x30
214	cmpw    r3,r5
215	bge     2f
2161:
217#ifdef	CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
218	lis	r3,toreset(enable_cpu_a011_workaround)@ha
219	lwz	r3,toreset(enable_cpu_a011_workaround)@l(r3)
220	cmpwi	r3,0
221	beq	2f
222#endif
223	mfspr	r3,L1CSR2
224	oris	r3,r3,(L1CSR2_DCWS)@h
225	mtspr	L1CSR2,r3
2262:
227#endif
228
229#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
230	/*
231	 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
232	 * write shadow mode. This code should run after other code setting
233	 * DCWS.
234	 */
235	mfspr	r3,L1CSR2
236	andis.	r3,r3,(L1CSR2_DCWS)@h
237	beq	1f
238	mfspr	r3, SPRN_HDBCR0
239	oris	r3, r3, 0x8000
240	mtspr	SPRN_HDBCR0, r3
2411:
242#endif
243
244#ifdef CONFIG_BACKSIDE_L2_CACHE
245	/* skip L2 setup on P2040/P2040E as they have no L2 */
246	mfspr	r3,SPRN_SVR
247	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */
248
249	lis	r3,SVR_P2040@h
250	ori	r3,r3,SVR_P2040@l
251	cmpw	r6,r3
252	beq 3f
253
254	/* Enable/invalidate the L2 cache */
255	msync
256	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
257	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
258	mtspr	SPRN_L2CSR0,r2
2591:
260	mfspr	r3,SPRN_L2CSR0
261	and.	r1,r3,r2
262	bne	1b
263
264#ifdef CONFIG_SYS_CACHE_STASHING
265	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
266	addi	r3,r8,1
267	mtspr	SPRN_L2CSR1,r3
268#endif
269
270	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
271	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
272	mtspr	SPRN_L2CSR0,r3
273	isync
2742:
275	mfspr	r3,SPRN_L2CSR0
276	andis.	r1,r3,L2CSR0_L2E@h
277	beq	2b
278#endif
2793:
280	/* setup mapping for the spin table, WIMGE=0b00100 */
281	lis	r13,toreset(__spin_table_addr)@h
282	ori	r13,r13,toreset(__spin_table_addr)@l
283	lwz	r13,0(r13)
284	/* mask by 4K */
285	rlwinm	r13,r13,0,0,19
286
287	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
288	mtspr	SPRN_MAS0,r11
289	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
290	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
291	mtspr	SPRN_MAS1,r11
292	oris	r11,r13,(MAS2_M|MAS2_G)@h
293	ori	r11,r13,(MAS2_M|MAS2_G)@l
294	mtspr	SPRN_MAS2,r11
295	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
296	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
297	mtspr	SPRN_MAS3,r11
298	li	r11,0
299	mtspr	SPRN_MAS7,r11
300	tlbwe
301
302	/*
303	 * __bootpg_addr has the address of __second_half_boot_page
304	 * jump there in AS=1 space with cache enabled
305	 */
306	lis	r13,toreset(__bootpg_addr)@h
307	ori	r13,r13,toreset(__bootpg_addr)@l
308	lwz	r11,0(r13)
309	mtspr	SPRN_SRR0,r11
310	mfmsr	r13
311	ori	r12,r13,MSR_IS|MSR_DS@l
312	mtspr	SPRN_SRR1,r12
313	rfi
314
315	/*
316	 * Allocate some space for the SDRAM address of the bootpg.
317	 * This variable has to be in the boot page so that it can
318	 * be accessed by secondary cores when they come out of reset.
319	 */
320	.align L1_CACHE_SHIFT
321	.globl __bootpg_addr
322__bootpg_addr:
323	.long	0
324
325	.global __spin_table_addr
326__spin_table_addr:
327	.long	0
328
329	/*
330	 * This variable is set by cpu_init_r() after parsing hwconfig
331	 * to enable workaround for erratum NMG_CPU_A011.
332	 */
333	.align L1_CACHE_SHIFT
334	.global enable_cpu_a011_workaround
335enable_cpu_a011_workaround:
336	.long	1
337
338	/* Fill in the empty space.  The actual reset vector is
339	 * the last word of the page */
340__secondary_start_code_end:
341	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
342__secondary_reset_vector:
343	b	__secondary_start_page
344
345
346/* this is a separated page for the spin table and cacheable boot code */
347	.align L1_CACHE_SHIFT
348	.global __second_half_boot_page
349__second_half_boot_page:
350#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
351	lis	r3,(spin_table_compat - __second_half_boot_page)@h
352	ori	r3,r3,(spin_table_compat - __second_half_boot_page)@l
353	add	r3,r3,r11 /* r11 has the address of __second_half_boot_page */
354	lwz	r14,0(r3)
355#endif
356
357#define ENTRY_ADDR_UPPER	0
358#define ENTRY_ADDR_LOWER	4
359#define ENTRY_R3_UPPER		8
360#define ENTRY_R3_LOWER		12
361#define ENTRY_RESV		16
362#define ENTRY_PIR		20
363#define ENTRY_SIZE		64
364	/*
365	 * setup the entry
366	 * r10 has the base address of the spin table.
367	 * spin table is defined as
368	 * struct {
369	 *	uint64_t entry_addr;
370	 *	uint64_t r3;
371	 *	uint32_t rsvd1;
372	 *	uint32_t pir;
373	 * };
374	 * we pad this struct to 64 bytes so each entry is in its own cacheline
375	 */
376	li	r3,0
377	li	r8,1
378	mfspr	r4,SPRN_PIR
379	stw	r3,ENTRY_ADDR_UPPER(r10)
380	stw	r3,ENTRY_R3_UPPER(r10)
381	stw	r4,ENTRY_R3_LOWER(r10)
382	stw	r3,ENTRY_RESV(r10)
383	stw	r4,ENTRY_PIR(r10)
384	msync
385	stw	r8,ENTRY_ADDR_LOWER(r10)
386
387	/* spin waiting for addr */
3883:
389/*
390 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
391 * memory. Old OS may not work with this change. A patch is waiting to be
392 * accepted for Linux kernel. Other OS needs similar fix to spin table.
393 * For OSes with old spin table code, we can enable this temporary fix by
394 * setting environmental variable "spin_table_compat". For new OSes, set
395 * "spin_table_compat=no". After Linux is fixed, we can remove this macro
396 * and related code. For now, it is enabled by default.
397 */
398#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
399	cmpwi   r14,0
400	beq     4f
401	dcbf    0, r10
402	sync
4034:
404#endif
405	lwz	r4,ENTRY_ADDR_LOWER(r10)
406	andi.	r11,r4,1
407	bne	3b
408	isync
409
410	/* setup IVORs to match fixed offsets */
411#include "fixed_ivor.S"
412
413	/* get the upper bits of the addr */
414	lwz	r11,ENTRY_ADDR_UPPER(r10)
415
416	/* setup branch addr */
417	mtspr	SPRN_SRR0,r4
418
419	/* mark the entry as released */
420	li	r8,3
421	stw	r8,ENTRY_ADDR_LOWER(r10)
422
423	/* mask by ~64M to setup our tlb we will jump to */
424	rlwinm	r12,r4,0,0,5
425
426	/*
427	 * setup r3, r4, r5, r6, r7, r8, r9
428	 * r3 contains the value to put in the r3 register at secondary cpu
429	 * entry. The high 32-bits are ignored on 32-bit chip implementations.
430	 * 64-bit chip implementations however shall load all 64-bits
431	 */
432#ifdef CONFIG_SYS_PPC64
433	ld	r3,ENTRY_R3_UPPER(r10)
434#else
435	lwz	r3,ENTRY_R3_LOWER(r10)
436#endif
437	li	r4,0
438	li	r5,0
439	li	r6,0
440	lis	r7,(64*1024*1024)@h
441	li	r8,0
442	li	r9,0
443
444	/* load up the pir */
445	lwz	r0,ENTRY_PIR(r10)
446	mtspr	SPRN_PIR,r0
447	mfspr	r0,SPRN_PIR
448	stw	r0,ENTRY_PIR(r10)
449
450	mtspr	IVPR,r12
451/*
452 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
453 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
454 * second mapping that maps addr 1:1 for 64M, and then we jump to
455 * addr
456 */
457	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
458	mtspr	SPRN_MAS0,r10
459	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
460	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
461	mtspr	SPRN_MAS1,r10
462	/* WIMGE = 0b00000 for now */
463	mtspr	SPRN_MAS2,r12
464	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
465	mtspr	SPRN_MAS3,r12
466#ifdef CONFIG_ENABLE_36BIT_PHYS
467	mtspr	SPRN_MAS7,r11
468#endif
469	tlbwe
470
471/* Now we have another mapping for this page, so we jump to that
472 * mapping
473 */
474	mtspr	SPRN_SRR1,r13
475	rfi
476
477
478	.align 6
479	.globl __spin_table
480__spin_table:
481	.space CONFIG_MAX_CPUS*ENTRY_SIZE
482
483#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
484	.align L1_CACHE_SHIFT
485	.global spin_table_compat
486spin_table_compat:
487	.long	1
488
489#endif
490
491__spin_table_end:
492	.space 4096 - (__spin_table_end - __spin_table)
493