1/*
2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc85xx.h>
27#include <version.h>
28
29#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36
37/* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page.  We then set up the core, and head to
42 * start_secondary.  Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
45 */
46	.globl	__secondary_start_page
47	.align	12
48__secondary_start_page:
49/* First do some preliminary setup */
50	lis	r3, HID0_EMCP@h		/* enable machine check */
51#ifndef CONFIG_E500MC
52	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
53#endif
54#ifdef CONFIG_PHYS_64BIT
55	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
56#endif
57	mtspr	SPRN_HID0,r3
58
59#ifndef CONFIG_E500MC
60	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
61	mfspr   r0,PVR
62	andi.	r0,r0,0xff
63	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
64	blt 1f
65	/* Set MBDD bit also */
66	ori r3, r3, HID1_MBDD@l
671:
68	mtspr	SPRN_HID1,r3
69#endif
70
71#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
72	mfspr	r3,SPRN_HDBCR1
73	oris	r3,r3,0x0100
74	mtspr	SPRN_HDBCR1,r3
75#endif
76
77#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
78	mfspr	r3,SPRN_SVR
79	rlwinm	r3,r3,0,0xff
80	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
81	cmpw	r3,r4
82	beq	1f
83
84#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
85	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
86	cmpw	r3,r4
87	beq	1f
88#endif
89
90	/* Not a supported revision affected by erratum */
91	b	2f
92
931:	/* Erratum says set bits 55:60 to 001001 */
94	msync
95	isync
96	mfspr	r3,SPRN_HDBCR0
97	li	r4,0x48
98	rlwimi	r3,r4,0,0x1f8
99	mtspr	SPRN_HDBCR0,r3
100	isync
1012:
102#endif
103
104	/* Enable branch prediction */
105	lis	r3,BUCSR_ENABLE@h
106	ori	r3,r3,BUCSR_ENABLE@l
107	mtspr	SPRN_BUCSR,r3
108
109	/* Ensure TB is 0 */
110	li	r3,0
111	mttbl	r3
112	mttbu	r3
113
114	/* Enable/invalidate the I-Cache */
115	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
116	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
117	mtspr	SPRN_L1CSR1,r2
1181:
119	mfspr	r3,SPRN_L1CSR1
120	and.	r1,r3,r2
121	bne	1b
122
123	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
124	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
125	mtspr	SPRN_L1CSR1,r3
126	isync
1272:
128	mfspr	r3,SPRN_L1CSR1
129	andi.	r1,r3,L1CSR1_ICE@l
130	beq	2b
131
132	/* Enable/invalidate the D-Cache */
133	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
134	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
135	mtspr	SPRN_L1CSR0,r2
1361:
137	mfspr	r3,SPRN_L1CSR0
138	and.	r1,r3,r2
139	bne	1b
140
141	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
142	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
143	mtspr	SPRN_L1CSR0,r3
144	isync
1452:
146	mfspr	r3,SPRN_L1CSR0
147	andi.	r1,r3,L1CSR0_DCE@l
148	beq	2b
149
150#define toreset(x) (x - __secondary_start_page + 0xfffff000)
151
152	/* get our PIR to figure out our table entry */
153	lis	r3,toreset(__spin_table_addr)@h
154	ori	r3,r3,toreset(__spin_table_addr)@l
155	lwz	r3,0(r3)
156
157	mfspr	r0,SPRN_PIR
158#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
159/*
160 * PIR definition for Chassis 2
161 * 0-17 Reserved (logic 0s)
162 * 18-19 CHIP_ID,    2'b00      - SoC 1
163 *                  all others - reserved
164 * 20-24 CLUSTER_ID 5'b00000   - CCM 1
165 *                  all others - reserved
166 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
167 *                       2'b01 - cluster 2
168 *                       2'b10 - cluster 3
169 *                       2'b11 - cluster 4
170 * 27-28 CORE_ID         2'b00 - core 0
171 *                       2'b01 - core 1
172 *                       2'b10 - core 2
173 *                       2'b11 - core 3
174 * 29-31 THREAD_ID       3'b000 - thread 0
175 *                       3'b001 - thread 1
176 *
177 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
178 * and clusters by 0x20.
179 *
180 * We renumber PIR so that all threads in the system are consecutive.
181 */
182
183	rlwinm	r8,r0,29,0x03	/* r8 = core within cluster */
184	srwi	r10,r0,5	/* r10 = cluster */
185
186	mulli	r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
187	add	r5,r5,r8	/* for spin table index */
188	mulli	r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE	/* for PIR */
189#elif	defined(CONFIG_E500MC)
190	rlwinm	r4,r0,27,27,31
191	mr	r5,r4
192#else
193	mr	r4,r0
194	mr	r5,r4
195#endif
196
197	/*
198	 * r10 has the base address for the entry.
199	 * we cannot access it yet before setting up a new TLB
200	 */
201	slwi	r8,r5,6	/* spin table is padded to 64 byte */
202	add	r10,r3,r8
203
204	mtspr	SPRN_PIR,r4	/* write to PIR register */
205
206#ifdef CONFIG_SYS_CACHE_STASHING
207	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
208	slwi	r8,r4,1
209	addi	r8,r8,32
210	mtspr	L1CSR2,r8
211#endif
212
213#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
214	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
215	/*
216	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
217	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
218	 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
219	 */
220	mfspr   r3,SPRN_SVR
221	rlwinm	r6,r3,24,~0x800		/* clear E bit */
222
223	lis	r5,SVR_P4080@h
224	ori	r5,r5,SVR_P4080@l
225	cmpw	r6,r5
226	bne	1f
227
228	rlwinm  r3,r3,0,0xf0
229	li      r5,0x30
230	cmpw    r3,r5
231	bge     2f
2321:
233#ifdef	CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
234	lis	r3,toreset(enable_cpu_a011_workaround)@ha
235	lwz	r3,toreset(enable_cpu_a011_workaround)@l(r3)
236	cmpwi	r3,0
237	beq	2f
238#endif
239	mfspr	r3,L1CSR2
240	oris	r3,r3,(L1CSR2_DCWS)@h
241	mtspr	L1CSR2,r3
2422:
243#endif
244
245#ifdef CONFIG_BACKSIDE_L2_CACHE
246	/* skip L2 setup on P2040/P2040E as they have no L2 */
247	mfspr	r3,SPRN_SVR
248	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */
249
250	lis	r3,SVR_P2040@h
251	ori	r3,r3,SVR_P2040@l
252	cmpw	r6,r3
253	beq 3f
254
255	/* Enable/invalidate the L2 cache */
256	msync
257	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
258	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
259	mtspr	SPRN_L2CSR0,r2
2601:
261	mfspr	r3,SPRN_L2CSR0
262	and.	r1,r3,r2
263	bne	1b
264
265#ifdef CONFIG_SYS_CACHE_STASHING
266	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
267	addi	r3,r8,1
268	mtspr	SPRN_L2CSR1,r3
269#endif
270
271	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
272	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
273	mtspr	SPRN_L2CSR0,r3
274	isync
2752:
276	mfspr	r3,SPRN_L2CSR0
277	andis.	r1,r3,L2CSR0_L2E@h
278	beq	2b
279#endif
2803:
281	/* setup mapping for the spin table, WIMGE=0b00100 */
282	lis	r13,toreset(__spin_table_addr)@h
283	ori	r13,r13,toreset(__spin_table_addr)@l
284	lwz	r13,0(r13)
285	/* mask by 4K */
286	rlwinm	r13,r13,0,0,19
287
288	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
289	mtspr	SPRN_MAS0,r11
290	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
291	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
292	mtspr	SPRN_MAS1,r11
293	oris	r11,r13,(MAS2_M|MAS2_G)@h
294	ori	r11,r13,(MAS2_M|MAS2_G)@l
295	mtspr	SPRN_MAS2,r11
296	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
297	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
298	mtspr	SPRN_MAS3,r11
299	li	r11,0
300	mtspr	SPRN_MAS7,r11
301	tlbwe
302
303	/*
304	 * __bootpg_addr has the address of __second_half_boot_page
305	 * jump there in AS=1 space with cache enabled
306	 */
307	lis	r13,toreset(__bootpg_addr)@h
308	ori	r13,r13,toreset(__bootpg_addr)@l
309	lwz	r11,0(r13)
310	mtspr	SPRN_SRR0,r11
311	mfmsr	r13
312	ori	r12,r13,MSR_IS|MSR_DS@l
313	mtspr	SPRN_SRR1,r12
314	rfi
315
316	/*
317	 * Allocate some space for the SDRAM address of the bootpg.
318	 * This variable has to be in the boot page so that it can
319	 * be accessed by secondary cores when they come out of reset.
320	 */
321	.align L1_CACHE_SHIFT
322	.globl __bootpg_addr
323__bootpg_addr:
324	.long	0
325
326	.global __spin_table_addr
327__spin_table_addr:
328	.long	0
329
330	/*
331	 * This variable is set by cpu_init_r() after parsing hwconfig
332	 * to enable workaround for erratum NMG_CPU_A011.
333	 */
334	.align L1_CACHE_SHIFT
335	.global enable_cpu_a011_workaround
336enable_cpu_a011_workaround:
337	.long	1
338
339	/* Fill in the empty space.  The actual reset vector is
340	 * the last word of the page */
341__secondary_start_code_end:
342	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
343__secondary_reset_vector:
344	b	__secondary_start_page
345
346
347/* this is a separated page for the spin table and cacheable boot code */
348	.align L1_CACHE_SHIFT
349	.global __second_half_boot_page
350__second_half_boot_page:
351#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
352	lis	r3,(spin_table_compat - __second_half_boot_page)@h
353	ori	r3,r3,(spin_table_compat - __second_half_boot_page)@l
354	add	r3,r3,r11 /* r11 has the address of __second_half_boot_page */
355	lwz	r14,0(r3)
356#endif
357
358#define ENTRY_ADDR_UPPER	0
359#define ENTRY_ADDR_LOWER	4
360#define ENTRY_R3_UPPER		8
361#define ENTRY_R3_LOWER		12
362#define ENTRY_RESV		16
363#define ENTRY_PIR		20
364#define ENTRY_SIZE		64
365	/*
366	 * setup the entry
367	 * r10 has the base address of the spin table.
368	 * spin table is defined as
369	 * struct {
370	 *	uint64_t entry_addr;
371	 *	uint64_t r3;
372	 *	uint32_t rsvd1;
373	 *	uint32_t pir;
374	 * };
375	 * we pad this struct to 64 bytes so each entry is in its own cacheline
376	 */
377	li	r3,0
378	li	r8,1
379	mfspr	r4,SPRN_PIR
380	stw	r3,ENTRY_ADDR_UPPER(r10)
381	stw	r3,ENTRY_R3_UPPER(r10)
382	stw	r4,ENTRY_R3_LOWER(r10)
383	stw	r3,ENTRY_RESV(r10)
384	stw	r4,ENTRY_PIR(r10)
385	msync
386	stw	r8,ENTRY_ADDR_LOWER(r10)
387
388	/* spin waiting for addr */
3893:
390/*
391 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
392 * memory. Old OS may not work with this change. A patch is waiting to be
393 * accepted for Linux kernel. Other OS needs similar fix to spin table.
394 * For OSes with old spin table code, we can enable this temporary fix by
395 * setting environmental variable "spin_table_compat". For new OSes, set
396 * "spin_table_compat=no". After Linux is fixed, we can remove this macro
397 * and related code. For now, it is enabled by default.
398 */
399#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
400	cmpwi   r14,0
401	beq     4f
402	dcbf    0, r10
403	sync
4044:
405#endif
406	lwz	r4,ENTRY_ADDR_LOWER(r10)
407	andi.	r11,r4,1
408	bne	3b
409	isync
410
411	/* setup IVORs to match fixed offsets */
412#include "fixed_ivor.S"
413
414	/* get the upper bits of the addr */
415	lwz	r11,ENTRY_ADDR_UPPER(r10)
416
417	/* setup branch addr */
418	mtspr	SPRN_SRR0,r4
419
420	/* mark the entry as released */
421	li	r8,3
422	stw	r8,ENTRY_ADDR_LOWER(r10)
423
424	/* mask by ~64M to setup our tlb we will jump to */
425	rlwinm	r12,r4,0,0,5
426
427	/*
428	 * setup r3, r4, r5, r6, r7, r8, r9
429	 * r3 contains the value to put in the r3 register at secondary cpu
430	 * entry. The high 32-bits are ignored on 32-bit chip implementations.
431	 * 64-bit chip implementations however shall load all 64-bits
432	 */
433#ifdef CONFIG_SYS_PPC64
434	ld	r3,ENTRY_R3_UPPER(r10)
435#else
436	lwz	r3,ENTRY_R3_LOWER(r10)
437#endif
438	li	r4,0
439	li	r5,0
440	li	r6,0
441	lis	r7,(64*1024*1024)@h
442	li	r8,0
443	li	r9,0
444
445	/* load up the pir */
446	lwz	r0,ENTRY_PIR(r10)
447	mtspr	SPRN_PIR,r0
448	mfspr	r0,SPRN_PIR
449	stw	r0,ENTRY_PIR(r10)
450
451	mtspr	IVPR,r12
452/*
453 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
454 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
455 * second mapping that maps addr 1:1 for 64M, and then we jump to
456 * addr
457 */
458	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
459	mtspr	SPRN_MAS0,r10
460	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
461	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
462	mtspr	SPRN_MAS1,r10
463	/* WIMGE = 0b00000 for now */
464	mtspr	SPRN_MAS2,r12
465	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
466	mtspr	SPRN_MAS3,r12
467#ifdef CONFIG_ENABLE_36BIT_PHYS
468	mtspr	SPRN_MAS7,r11
469#endif
470	tlbwe
471
472/* Now we have another mapping for this page, so we jump to that
473 * mapping
474 */
475	mtspr	SPRN_SRR1,r13
476	rfi
477
478
479	.align 6
480	.globl __spin_table
481__spin_table:
482	.space CONFIG_MAX_CPUS*ENTRY_SIZE
483
484#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
485	.align L1_CACHE_SHIFT
486	.global spin_table_compat
487spin_table_compat:
488	.long	1
489
490#endif
491
492__spin_table_end:
493	.space 4096 - (__spin_table_end - __spin_table)
494