1/*
2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <asm-offsets.h>
25#include <config.h>
26#include <mpc85xx.h>
27#include <version.h>
28
29#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33
34#include <asm/cache.h>
35#include <asm/mmu.h>
36
37/* To boot secondary cpus, we need a place for them to start up.
38 * Normally, they start at 0xfffffffc, but that's usually the
39 * firmware, and we don't want to have to run the firmware again.
40 * Instead, the primary cpu will set the BPTR to point here to
41 * this page.  We then set up the core, and head to
42 * start_secondary.  Note that this means that the code below
43 * must never exceed 1023 instructions (the branch at the end
44 * would then be the 1024th).
45 */
46	.globl	__secondary_start_page
47	.align	12
48__secondary_start_page:
49/* First do some preliminary setup */
50	lis	r3, HID0_EMCP@h		/* enable machine check */
51#ifndef CONFIG_E500MC
52	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
53#endif
54#ifdef CONFIG_PHYS_64BIT
55	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
56#endif
57	mtspr	SPRN_HID0,r3
58
59#ifndef CONFIG_E500MC
60	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
61	mfspr   r0,PVR
62	andi.	r0,r0,0xff
63	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
64	blt 1f
65	/* Set MBDD bit also */
66	ori r3, r3, HID1_MBDD@l
671:
68	mtspr	SPRN_HID1,r3
69#endif
70
71#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
72	mfspr	r3,977
73	oris	r3,r3,0x0100
74	mtspr	977,r3
75#endif
76
77#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
78	mfspr	r3,SPRN_SVR
79	rlwinm	r3,r3,0,0xff
80	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
81	cmpw	r3,r4
82	beq	1f
83
84#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
85	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
86	cmpw	r3,r4
87	beq	1f
88#endif
89
90	/* Not a supported revision affected by erratum */
91	b	2f
92
931:	/* Erratum says set bits 55:60 to 001001 */
94	msync
95	isync
96	mfspr	r3,976
97	li	r4,0x48
98	rlwimi	r3,r4,0,0x1f8
99	mtspr	976,r3
100	isync
1012:
102#endif
103
104	/* Enable branch prediction */
105	lis	r3,BUCSR_ENABLE@h
106	ori	r3,r3,BUCSR_ENABLE@l
107	mtspr	SPRN_BUCSR,r3
108
109	/* Ensure TB is 0 */
110	li	r3,0
111	mttbl	r3
112	mttbu	r3
113
114	/* Enable/invalidate the I-Cache */
115	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
116	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
117	mtspr	SPRN_L1CSR1,r2
1181:
119	mfspr	r3,SPRN_L1CSR1
120	and.	r1,r3,r2
121	bne	1b
122
123	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
124	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
125	mtspr	SPRN_L1CSR1,r3
126	isync
1272:
128	mfspr	r3,SPRN_L1CSR1
129	andi.	r1,r3,L1CSR1_ICE@l
130	beq	2b
131
132	/* Enable/invalidate the D-Cache */
133	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
134	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
135	mtspr	SPRN_L1CSR0,r2
1361:
137	mfspr	r3,SPRN_L1CSR0
138	and.	r1,r3,r2
139	bne	1b
140
141	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
142	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
143	mtspr	SPRN_L1CSR0,r3
144	isync
1452:
146	mfspr	r3,SPRN_L1CSR0
147	andi.	r1,r3,L1CSR0_DCE@l
148	beq	2b
149
150#define toreset(x) (x - __secondary_start_page + 0xfffff000)
151
152	/* get our PIR to figure out our table entry */
153	lis	r3,toreset(__spin_table)@h
154	ori	r3,r3,toreset(__spin_table)@l
155
156	/* r10 has the base address for the entry */
157	mfspr	r0,SPRN_PIR
158#if	defined(CONFIG_E6500)
159/*
160 * PIR definition for E6500
161 * 0-17 Reserved (logic 0s)
162 * 8-19 CHIP_ID,    2’b00      - SoC 1
163 *                  all others - reserved
164 * 20-24 CLUSTER_ID 5’b00000   - CCM 1
165 *                  all others - reserved
166 * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1
167 *                       2’b01 - cluster 2
168 *                       2’b10 - cluster 3
169 *                       2’b11 - cluster 4
170 * 27-28 CORE_ID         2’b00 - core 0
171 *                       2’b01 - core 1
172 *                       2’b10 - core 2
173 *                       2’b11 - core 3
174 * 29-31 THREAD_ID       3’b000 - thread 0
175 *                       3’b001 - thread 1
176 */
177	rlwinm  r4,r0,29,25,31
178#elif	defined(CONFIG_E500MC)
179	rlwinm	r4,r0,27,27,31
180#else
181	mr	r4,r0
182#endif
183	slwi	r8,r4,5
184	add	r10,r3,r8
185
186#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
187	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
188	slwi	r8,r4,1
189	addi	r8,r8,32
190	mtspr	L1CSR2,r8
191#endif
192
193#ifdef CONFIG_E6500
194	mfspr	r0,SPRN_PIR
195	/*
196	 * core 0 thread 0: pir reset value 0x00, new pir 0
197	 * core 0 thread 1: pir reset value 0x01, new pir 1
198	 * core 1 thread 0: pir reset value 0x08, new pir 2
199	 * core 1 thread 1: pir reset value 0x09, new pir 3
200	 * core 2 thread 0: pir reset value 0x10, new pir 4
201	 * core 2 thread 1: pir reset value 0x11, new pir 5
202	 * etc.
203	 *
204	 * Only thread 0 of each core will be running, updating PIR doesn't
205	 * need to deal with the thread bits.
206	 */
207	rlwinm	r4,r0,30,24,30
208#endif
209
210	mtspr	SPRN_PIR,r4	/* write to PIR register */
211
212#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
213	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
214	/*
215	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
216	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
217	 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
218	 */
219	mfspr   r3,SPRN_SVR
220	rlwinm	r6,r3,24,~0x800		/* clear E bit */
221
222	lis	r5,SVR_P4080@h
223	ori	r5,r5,SVR_P4080@l
224	cmpw	r6,r5
225	bne	1f
226
227	rlwinm  r3,r3,0,0xf0
228	li      r5,0x30
229	cmpw    r3,r5
230	bge     2f
2311:
232#ifdef	CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
233	lis	r3,toreset(enable_cpu_a011_workaround)@ha
234	lwz	r3,toreset(enable_cpu_a011_workaround)@l(r3)
235	cmpwi	r3,0
236	beq	2f
237#endif
238	mfspr	r3,L1CSR2
239	oris	r3,r3,(L1CSR2_DCWS)@h
240	mtspr	L1CSR2,r3
2412:
242#endif
243
244#ifdef CONFIG_BACKSIDE_L2_CACHE
245	/* skip L2 setup on P2040/P2040E as they have no L2 */
246	mfspr	r3,SPRN_SVR
247	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */
248
249	lis	r3,SVR_P2040@h
250	ori	r3,r3,SVR_P2040@l
251	cmpw	r6,r3
252	beq 3f
253
254	/* Enable/invalidate the L2 cache */
255	msync
256	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
257	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
258	mtspr	SPRN_L2CSR0,r2
2591:
260	mfspr	r3,SPRN_L2CSR0
261	and.	r1,r3,r2
262	bne	1b
263
264#ifdef CONFIG_SYS_CACHE_STASHING
265	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
266	addi	r3,r8,1
267	mtspr	SPRN_L2CSR1,r3
268#endif
269
270	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
271	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
272	mtspr	SPRN_L2CSR0,r3
273	isync
2742:
275	mfspr	r3,SPRN_L2CSR0
276	andis.	r1,r3,L2CSR0_L2E@h
277	beq	2b
278#endif
2793:
280
281#define EPAPR_MAGIC		(0x45504150)
282#define ENTRY_ADDR_UPPER	0
283#define ENTRY_ADDR_LOWER	4
284#define ENTRY_R3_UPPER		8
285#define ENTRY_R3_LOWER		12
286#define ENTRY_RESV		16
287#define ENTRY_PIR		20
288#define ENTRY_R6_UPPER		24
289#define ENTRY_R6_LOWER		28
290#define ENTRY_SIZE		32
291
292	/* setup the entry */
293	li	r3,0
294	li	r8,1
295	stw	r4,ENTRY_PIR(r10)
296	stw	r3,ENTRY_ADDR_UPPER(r10)
297	stw	r8,ENTRY_ADDR_LOWER(r10)
298	stw	r3,ENTRY_R3_UPPER(r10)
299	stw	r4,ENTRY_R3_LOWER(r10)
300	stw	r3,ENTRY_R6_UPPER(r10)
301	stw	r3,ENTRY_R6_LOWER(r10)
302
303	/* load r13 with the address of the 'bootpg' in SDRAM */
304	lis	r13,toreset(__bootpg_addr)@h
305	ori	r13,r13,toreset(__bootpg_addr)@l
306	lwz	r13,0(r13)
307
308	/* setup mapping for AS = 1, and jump there */
309	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
310	mtspr	SPRN_MAS0,r11
311	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
312	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
313	mtspr	SPRN_MAS1,r11
314	oris	r11,r13,(MAS2_I|MAS2_G)@h
315	ori	r11,r13,(MAS2_I|MAS2_G)@l
316	mtspr	SPRN_MAS2,r11
317	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
318	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
319	mtspr	SPRN_MAS3,r11
320	tlbwe
321
322	bl	1f
3231:	mflr	r11
324	/*
325	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
326	 * this mask to fixup the cpu spin table and the address that we want
327	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
328	 * bootpg is at 0x7ffff000 in SDRAM.
329	 */
330	ori	r13,r13,0xfff
331	and	r11, r11, r13
332	and	r10, r10, r13
333
334	addi	r11,r11,(2f-1b)
335	mfmsr	r13
336	ori	r12,r13,MSR_IS|MSR_DS@l
337
338	mtspr	SPRN_SRR0,r11
339	mtspr	SPRN_SRR1,r12
340	rfi
341
342	/* spin waiting for addr */
3432:
344	lwz	r4,ENTRY_ADDR_LOWER(r10)
345	andi.	r11,r4,1
346	bne	2b
347	isync
348
349	/* setup IVORs to match fixed offsets */
350#include "fixed_ivor.S"
351
352	/* get the upper bits of the addr */
353	lwz	r11,ENTRY_ADDR_UPPER(r10)
354
355	/* setup branch addr */
356	mtspr	SPRN_SRR0,r4
357
358	/* mark the entry as released */
359	li	r8,3
360	stw	r8,ENTRY_ADDR_LOWER(r10)
361
362	/* mask by ~64M to setup our tlb we will jump to */
363	rlwinm	r12,r4,0,0,5
364
365	/* setup r3, r4, r5, r6, r7, r8, r9 */
366	lwz	r3,ENTRY_R3_LOWER(r10)
367	li	r4,0
368	li	r5,0
369	lwz	r6,ENTRY_R6_LOWER(r10)
370	lis	r7,(64*1024*1024)@h
371	li	r8,0
372	li	r9,0
373
374	/* load up the pir */
375	lwz	r0,ENTRY_PIR(r10)
376	mtspr	SPRN_PIR,r0
377	mfspr	r0,SPRN_PIR
378	stw	r0,ENTRY_PIR(r10)
379
380	mtspr	IVPR,r12
381/*
382 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
383 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
384 * second mapping that maps addr 1:1 for 64M, and then we jump to
385 * addr
386 */
387	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
388	mtspr	SPRN_MAS0,r10
389	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
390	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
391	mtspr	SPRN_MAS1,r10
392	/* WIMGE = 0b00000 for now */
393	mtspr	SPRN_MAS2,r12
394	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
395	mtspr	SPRN_MAS3,r12
396#ifdef CONFIG_ENABLE_36BIT_PHYS
397	mtspr	SPRN_MAS7,r11
398#endif
399	tlbwe
400
401/* Now we have another mapping for this page, so we jump to that
402 * mapping
403 */
404	mtspr	SPRN_SRR1,r13
405	rfi
406
407	/*
408	 * Allocate some space for the SDRAM address of the bootpg.
409	 * This variable has to be in the boot page so that it can
410	 * be accessed by secondary cores when they come out of reset.
411	 */
412	.globl __bootpg_addr
413__bootpg_addr:
414	.long	0
415
416	.align L1_CACHE_SHIFT
417	.globl __spin_table
418__spin_table:
419	.space CONFIG_MAX_CPUS*ENTRY_SIZE
420
421	/*
422	 * This variable is set by cpu_init_r() after parsing hwconfig
423	 * to enable workaround for erratum NMG_CPU_A011.
424	 */
425	.align L1_CACHE_SHIFT
426	.global enable_cpu_a011_workaround
427enable_cpu_a011_workaround:
428	.long	1
429
430	/* Fill in the empty space.  The actual reset vector is
431	 * the last word of the page */
432__secondary_start_code_end:
433	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
434__secondary_reset_vector:
435	b	__secondary_start_page
436