1/* 2 * Copyright 2008-2012 Freescale Semiconductor, Inc. 3 * Kumar Gala <kumar.gala@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#include <asm-offsets.h> 9#include <config.h> 10#include <mpc85xx.h> 11#include <version.h> 12 13#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 14 15#include <ppc_asm.tmpl> 16#include <ppc_defs.h> 17 18#include <asm/cache.h> 19#include <asm/mmu.h> 20 21/* To boot secondary cpus, we need a place for them to start up. 22 * Normally, they start at 0xfffffffc, but that's usually the 23 * firmware, and we don't want to have to run the firmware again. 24 * Instead, the primary cpu will set the BPTR to point here to 25 * this page. We then set up the core, and head to 26 * start_secondary. Note that this means that the code below 27 * must never exceed 1023 instructions (the branch at the end 28 * would then be the 1024th). 29 */ 30 .globl __secondary_start_page 31 .align 12 32__secondary_start_page: 33/* First do some preliminary setup */ 34 lis r3, HID0_EMCP@h /* enable machine check */ 35#ifndef CONFIG_E500MC 36 ori r3,r3,HID0_TBEN@l /* enable Timebase */ 37#endif 38#ifdef CONFIG_PHYS_64BIT 39 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ 40#endif 41 mtspr SPRN_HID0,r3 42 43#ifndef CONFIG_E500MC 44 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 45 mfspr r0,PVR 46 andi. r0,r0,0xff 47 cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ 48 blt 1f 49 /* Set MBDD bit also */ 50 ori r3, r3, HID1_MBDD@l 511: 52 mtspr SPRN_HID1,r3 53#endif 54 55#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 56 mfspr r3,SPRN_HDBCR1 57 oris r3,r3,0x0100 58 mtspr SPRN_HDBCR1,r3 59#endif 60 61#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 62 mfspr r3,SPRN_SVR 63 rlwinm r3,r3,0,0xff 64 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 65 cmpw r3,r4 66 beq 1f 67 68#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 69 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 70 cmpw r3,r4 71 beq 1f 72#endif 73 74 /* Not a supported revision affected by erratum */ 75 b 2f 76 771: /* Erratum says set bits 55:60 to 001001 */ 78 msync 79 isync 80 mfspr r3,SPRN_HDBCR0 81 li r4,0x48 82 rlwimi r3,r4,0,0x1f8 83 mtspr SPRN_HDBCR0,r3 84 isync 852: 86#endif 87 88 /* Enable branch prediction */ 89 lis r3,BUCSR_ENABLE@h 90 ori r3,r3,BUCSR_ENABLE@l 91 mtspr SPRN_BUCSR,r3 92 93 /* Ensure TB is 0 */ 94 li r3,0 95 mttbl r3 96 mttbu r3 97 98 /* Enable/invalidate the I-Cache */ 99 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 100 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 101 mtspr SPRN_L1CSR1,r2 1021: 103 mfspr r3,SPRN_L1CSR1 104 and. r1,r3,r2 105 bne 1b 106 107 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 108 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 109 mtspr SPRN_L1CSR1,r3 110 isync 1112: 112 mfspr r3,SPRN_L1CSR1 113 andi. r1,r3,L1CSR1_ICE@l 114 beq 2b 115 116 /* Enable/invalidate the D-Cache */ 117 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 118 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 119 mtspr SPRN_L1CSR0,r2 1201: 121 mfspr r3,SPRN_L1CSR0 122 and. r1,r3,r2 123 bne 1b 124 125 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 126 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 127 mtspr SPRN_L1CSR0,r3 128 isync 1292: 130 mfspr r3,SPRN_L1CSR0 131 andi. r1,r3,L1CSR0_DCE@l 132 beq 2b 133 134#define toreset(x) (x - __secondary_start_page + 0xfffff000) 135 136 /* get our PIR to figure out our table entry */ 137 lis r3,toreset(__spin_table_addr)@h 138 ori r3,r3,toreset(__spin_table_addr)@l 139 lwz r3,0(r3) 140 141 mfspr r0,SPRN_PIR 142#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 143/* 144 * PIR definition for Chassis 2 145 * 0-17 Reserved (logic 0s) 146 * 18-19 CHIP_ID, 2'b00 - SoC 1 147 * all others - reserved 148 * 20-24 CLUSTER_ID 5'b00000 - CCM 1 149 * all others - reserved 150 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1 151 * 2'b01 - cluster 2 152 * 2'b10 - cluster 3 153 * 2'b11 - cluster 4 154 * 27-28 CORE_ID 2'b00 - core 0 155 * 2'b01 - core 1 156 * 2'b10 - core 2 157 * 2'b11 - core 3 158 * 29-31 THREAD_ID 3'b000 - thread 0 159 * 3'b001 - thread 1 160 * 161 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08 162 * and clusters by 0x20. 163 * 164 * We renumber PIR so that all threads in the system are consecutive. 165 */ 166 167 rlwinm r8,r0,29,0x03 /* r8 = core within cluster */ 168 srwi r10,r0,5 /* r10 = cluster */ 169 170 mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER 171 add r5,r5,r8 /* for spin table index */ 172 mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */ 173#elif defined(CONFIG_E500MC) 174 rlwinm r4,r0,27,27,31 175 mr r5,r4 176#else 177 mr r4,r0 178 mr r5,r4 179#endif 180 181 /* 182 * r10 has the base address for the entry. 183 * we cannot access it yet before setting up a new TLB 184 */ 185 slwi r8,r5,6 /* spin table is padded to 64 byte */ 186 add r10,r3,r8 187 188 mtspr SPRN_PIR,r4 /* write to PIR register */ 189 190#ifdef CONFIG_SYS_CACHE_STASHING 191 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 192 slwi r8,r4,1 193 addi r8,r8,32 194 mtspr L1CSR2,r8 195#endif 196 197#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 198 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 199 /* 200 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 201 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 202 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 203 */ 204 mfspr r3,SPRN_SVR 205 rlwinm r6,r3,24,~0x800 /* clear E bit */ 206 207 lis r5,SVR_P4080@h 208 ori r5,r5,SVR_P4080@l 209 cmpw r6,r5 210 bne 1f 211 212 rlwinm r3,r3,0,0xf0 213 li r5,0x30 214 cmpw r3,r5 215 bge 2f 2161: 217#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 218 lis r3,toreset(enable_cpu_a011_workaround)@ha 219 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3) 220 cmpwi r3,0 221 beq 2f 222#endif 223 mfspr r3,L1CSR2 224 oris r3,r3,(L1CSR2_DCWS)@h 225 mtspr L1CSR2,r3 2262: 227#endif 228 229#ifdef CONFIG_BACKSIDE_L2_CACHE 230 /* skip L2 setup on P2040/P2040E as they have no L2 */ 231 mfspr r3,SPRN_SVR 232 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */ 233 234 lis r3,SVR_P2040@h 235 ori r3,r3,SVR_P2040@l 236 cmpw r6,r3 237 beq 3f 238 239 /* Enable/invalidate the L2 cache */ 240 msync 241 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h 242 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l 243 mtspr SPRN_L2CSR0,r2 2441: 245 mfspr r3,SPRN_L2CSR0 246 and. r1,r3,r2 247 bne 1b 248 249#ifdef CONFIG_SYS_CACHE_STASHING 250 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 251 addi r3,r8,1 252 mtspr SPRN_L2CSR1,r3 253#endif 254 255 lis r3,CONFIG_SYS_INIT_L2CSR0@h 256 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l 257 mtspr SPRN_L2CSR0,r3 258 isync 2592: 260 mfspr r3,SPRN_L2CSR0 261 andis. r1,r3,L2CSR0_L2E@h 262 beq 2b 263#endif 2643: 265 /* setup mapping for the spin table, WIMGE=0b00100 */ 266 lis r13,toreset(__spin_table_addr)@h 267 ori r13,r13,toreset(__spin_table_addr)@l 268 lwz r13,0(r13) 269 /* mask by 4K */ 270 rlwinm r13,r13,0,0,19 271 272 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h 273 mtspr SPRN_MAS0,r11 274 lis r11,(MAS1_VALID|MAS1_IPROT)@h 275 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l 276 mtspr SPRN_MAS1,r11 277 oris r11,r13,(MAS2_M|MAS2_G)@h 278 ori r11,r13,(MAS2_M|MAS2_G)@l 279 mtspr SPRN_MAS2,r11 280 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h 281 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l 282 mtspr SPRN_MAS3,r11 283 li r11,0 284 mtspr SPRN_MAS7,r11 285 tlbwe 286 287 /* 288 * __bootpg_addr has the address of __second_half_boot_page 289 * jump there in AS=1 space with cache enabled 290 */ 291 lis r13,toreset(__bootpg_addr)@h 292 ori r13,r13,toreset(__bootpg_addr)@l 293 lwz r11,0(r13) 294 mtspr SPRN_SRR0,r11 295 mfmsr r13 296 ori r12,r13,MSR_IS|MSR_DS@l 297 mtspr SPRN_SRR1,r12 298 rfi 299 300 /* 301 * Allocate some space for the SDRAM address of the bootpg. 302 * This variable has to be in the boot page so that it can 303 * be accessed by secondary cores when they come out of reset. 304 */ 305 .align L1_CACHE_SHIFT 306 .globl __bootpg_addr 307__bootpg_addr: 308 .long 0 309 310 .global __spin_table_addr 311__spin_table_addr: 312 .long 0 313 314 /* 315 * This variable is set by cpu_init_r() after parsing hwconfig 316 * to enable workaround for erratum NMG_CPU_A011. 317 */ 318 .align L1_CACHE_SHIFT 319 .global enable_cpu_a011_workaround 320enable_cpu_a011_workaround: 321 .long 1 322 323 /* Fill in the empty space. The actual reset vector is 324 * the last word of the page */ 325__secondary_start_code_end: 326 .space 4092 - (__secondary_start_code_end - __secondary_start_page) 327__secondary_reset_vector: 328 b __secondary_start_page 329 330 331/* this is a separated page for the spin table and cacheable boot code */ 332 .align L1_CACHE_SHIFT 333 .global __second_half_boot_page 334__second_half_boot_page: 335#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE 336 lis r3,(spin_table_compat - __second_half_boot_page)@h 337 ori r3,r3,(spin_table_compat - __second_half_boot_page)@l 338 add r3,r3,r11 /* r11 has the address of __second_half_boot_page */ 339 lwz r14,0(r3) 340#endif 341 342#define ENTRY_ADDR_UPPER 0 343#define ENTRY_ADDR_LOWER 4 344#define ENTRY_R3_UPPER 8 345#define ENTRY_R3_LOWER 12 346#define ENTRY_RESV 16 347#define ENTRY_PIR 20 348#define ENTRY_SIZE 64 349 /* 350 * setup the entry 351 * r10 has the base address of the spin table. 352 * spin table is defined as 353 * struct { 354 * uint64_t entry_addr; 355 * uint64_t r3; 356 * uint32_t rsvd1; 357 * uint32_t pir; 358 * }; 359 * we pad this struct to 64 bytes so each entry is in its own cacheline 360 */ 361 li r3,0 362 li r8,1 363 mfspr r4,SPRN_PIR 364 stw r3,ENTRY_ADDR_UPPER(r10) 365 stw r3,ENTRY_R3_UPPER(r10) 366 stw r4,ENTRY_R3_LOWER(r10) 367 stw r3,ENTRY_RESV(r10) 368 stw r4,ENTRY_PIR(r10) 369 msync 370 stw r8,ENTRY_ADDR_LOWER(r10) 371 372 /* spin waiting for addr */ 3733: 374/* 375 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled 376 * memory. Old OS may not work with this change. A patch is waiting to be 377 * accepted for Linux kernel. Other OS needs similar fix to spin table. 378 * For OSes with old spin table code, we can enable this temporary fix by 379 * setting environmental variable "spin_table_compat". For new OSes, set 380 * "spin_table_compat=no". After Linux is fixed, we can remove this macro 381 * and related code. For now, it is enabled by default. 382 */ 383#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE 384 cmpwi r14,0 385 beq 4f 386 dcbf 0, r10 387 sync 3884: 389#endif 390 lwz r4,ENTRY_ADDR_LOWER(r10) 391 andi. r11,r4,1 392 bne 3b 393 isync 394 395 /* setup IVORs to match fixed offsets */ 396#include "fixed_ivor.S" 397 398 /* get the upper bits of the addr */ 399 lwz r11,ENTRY_ADDR_UPPER(r10) 400 401 /* setup branch addr */ 402 mtspr SPRN_SRR0,r4 403 404 /* mark the entry as released */ 405 li r8,3 406 stw r8,ENTRY_ADDR_LOWER(r10) 407 408 /* mask by ~64M to setup our tlb we will jump to */ 409 rlwinm r12,r4,0,0,5 410 411 /* 412 * setup r3, r4, r5, r6, r7, r8, r9 413 * r3 contains the value to put in the r3 register at secondary cpu 414 * entry. The high 32-bits are ignored on 32-bit chip implementations. 415 * 64-bit chip implementations however shall load all 64-bits 416 */ 417#ifdef CONFIG_SYS_PPC64 418 ld r3,ENTRY_R3_UPPER(r10) 419#else 420 lwz r3,ENTRY_R3_LOWER(r10) 421#endif 422 li r4,0 423 li r5,0 424 li r6,0 425 lis r7,(64*1024*1024)@h 426 li r8,0 427 li r9,0 428 429 /* load up the pir */ 430 lwz r0,ENTRY_PIR(r10) 431 mtspr SPRN_PIR,r0 432 mfspr r0,SPRN_PIR 433 stw r0,ENTRY_PIR(r10) 434 435 mtspr IVPR,r12 436/* 437 * Coming here, we know the cpu has one TLB mapping in TLB1[0] 438 * which maps 0xfffff000-0xffffffff one-to-one. We set up a 439 * second mapping that maps addr 1:1 for 64M, and then we jump to 440 * addr 441 */ 442 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h 443 mtspr SPRN_MAS0,r10 444 lis r10,(MAS1_VALID|MAS1_IPROT)@h 445 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l 446 mtspr SPRN_MAS1,r10 447 /* WIMGE = 0b00000 for now */ 448 mtspr SPRN_MAS2,r12 449 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR) 450 mtspr SPRN_MAS3,r12 451#ifdef CONFIG_ENABLE_36BIT_PHYS 452 mtspr SPRN_MAS7,r11 453#endif 454 tlbwe 455 456/* Now we have another mapping for this page, so we jump to that 457 * mapping 458 */ 459 mtspr SPRN_SRR1,r13 460 rfi 461 462 463 .align 6 464 .globl __spin_table 465__spin_table: 466 .space CONFIG_MAX_CPUS*ENTRY_SIZE 467 468#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE 469 .align L1_CACHE_SHIFT 470 .global spin_table_compat 471spin_table_compat: 472 .long 1 473 474#endif 475 476__spin_table_end: 477 .space 4096 - (__spin_table_end - __spin_table) 478