1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2a47a12beSStefan Roese /*
3a47a12beSStefan Roese * Copyright (C) 2006 Freescale Semiconductor, Inc.
4a47a12beSStefan Roese *
5a47a12beSStefan Roese * Dave Liu <daveliu@freescale.com>
6a47a12beSStefan Roese * based on source code of Shlomi Gridish
7a47a12beSStefan Roese */
8a47a12beSStefan Roese
9b5bf5cb3SMasahiro Yamada #include <common.h>
101221ce45SMasahiro Yamada #include <linux/errno.h>
11b5bf5cb3SMasahiro Yamada #include <asm/io.h>
12b5bf5cb3SMasahiro Yamada #include <asm/immap_85xx.h>
13a47a12beSStefan Roese
142a44efebSZhao Qiang #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
15a47a12beSStefan Roese #define NUM_OF_PINS 32
qe_config_iopin(u8 port,u8 pin,int dir,int open_drain,int assign)16a47a12beSStefan Roese void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
17a47a12beSStefan Roese {
18a47a12beSStefan Roese u32 pin_2bit_mask;
19a47a12beSStefan Roese u32 pin_2bit_dir;
20a47a12beSStefan Roese u32 pin_2bit_assign;
21a47a12beSStefan Roese u32 pin_1bit_mask;
22a47a12beSStefan Roese u32 tmp_val;
23a47a12beSStefan Roese volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
24a47a12beSStefan Roese volatile par_io_t *par_io = (volatile par_io_t *)
25a47a12beSStefan Roese &(gur->qe_par_io);
26a47a12beSStefan Roese
27a47a12beSStefan Roese /* Caculate pin location and 2bit mask and dir */
28a47a12beSStefan Roese pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
29a47a12beSStefan Roese pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
30a47a12beSStefan Roese
31a47a12beSStefan Roese /* Setup the direction */
32a47a12beSStefan Roese tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
33a47a12beSStefan Roese in_be32(&par_io[port].cpdir2) :
34a47a12beSStefan Roese in_be32(&par_io[port].cpdir1);
35a47a12beSStefan Roese
36a47a12beSStefan Roese if (pin > (NUM_OF_PINS/2) -1) {
37a47a12beSStefan Roese out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val);
38a47a12beSStefan Roese out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val);
39a47a12beSStefan Roese } else {
40a47a12beSStefan Roese out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val);
41a47a12beSStefan Roese out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val);
42a47a12beSStefan Roese }
43a47a12beSStefan Roese
44a47a12beSStefan Roese /* Calculate pin location for 1bit mask */
45a47a12beSStefan Roese pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
46a47a12beSStefan Roese
47a47a12beSStefan Roese /* Setup the open drain */
48a47a12beSStefan Roese tmp_val = in_be32(&par_io[port].cpodr);
49a47a12beSStefan Roese if (open_drain)
50a47a12beSStefan Roese out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val);
51a47a12beSStefan Roese else
52a47a12beSStefan Roese out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val);
53a47a12beSStefan Roese
54a47a12beSStefan Roese /* Setup the assignment */
55a47a12beSStefan Roese tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
56a47a12beSStefan Roese in_be32(&par_io[port].cppar2):
57a47a12beSStefan Roese in_be32(&par_io[port].cppar1);
58a47a12beSStefan Roese pin_2bit_assign = (u32)(assign
59a47a12beSStefan Roese << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
60a47a12beSStefan Roese
61a47a12beSStefan Roese /* Clear and set 2 bits mask */
62a47a12beSStefan Roese if (pin > (NUM_OF_PINS/2) - 1) {
63a47a12beSStefan Roese out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val);
64a47a12beSStefan Roese out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val);
65a47a12beSStefan Roese } else {
66a47a12beSStefan Roese out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val);
67a47a12beSStefan Roese out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val);
68a47a12beSStefan Roese }
69a47a12beSStefan Roese }
70a47a12beSStefan Roese
71a47a12beSStefan Roese #endif /* CONFIG_QE */
72