1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * Copyright (C) 2003 Motorola Inc. 4 * Xianghua Xiao (x.xiao@motorola.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * PCI Configuration space access support for MPC85xx PCI Bridge 27 */ 28 #include <common.h> 29 #include <asm/cpm_85xx.h> 30 #include <pci.h> 31 32 #if !defined(CONFIG_FSL_PCI_INIT) 33 34 #ifndef CONFIG_SYS_PCI1_MEM_BUS 35 #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE 36 #endif 37 38 #ifndef CONFIG_SYS_PCI1_IO_BUS 39 #define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE 40 #endif 41 42 #ifndef CONFIG_SYS_PCI2_MEM_BUS 43 #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE 44 #endif 45 46 #ifndef CONFIG_SYS_PCI2_IO_BUS 47 #define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE 48 #endif 49 50 static struct pci_controller *pci_hose; 51 52 void 53 pci_mpc85xx_init(struct pci_controller *board_hose) 54 { 55 u16 reg16; 56 u32 dev; 57 58 volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); 59 #ifdef CONFIG_MPC85XX_PCI2 60 volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR); 61 #endif 62 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 63 struct pci_controller * hose; 64 65 pci_hose = board_hose; 66 67 hose = &pci_hose[0]; 68 69 hose->first_busno = 0; 70 hose->last_busno = 0xff; 71 72 pci_setup_indirect(hose, 73 (CONFIG_SYS_IMMR+0x8000), 74 (CONFIG_SYS_IMMR+0x8004)); 75 76 /* 77 * Hose scan. 78 */ 79 dev = PCI_BDF(hose->first_busno, 0, 0); 80 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 81 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 82 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 83 84 /* 85 * Clear non-reserved bits in status register. 86 */ 87 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 88 89 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { 90 /* PCI-X init */ 91 if (CONFIG_SYS_CLK_FREQ < 66000000) 92 printf("PCI-X will only work at 66 MHz\n"); 93 94 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 95 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 96 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); 97 } 98 99 pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff; 100 pcix->potear1 = 0x00000000; 101 pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff; 102 pcix->powbear1 = 0x00000000; 103 pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | 104 POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1)); 105 106 pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff; 107 pcix->potear2 = 0x00000000; 108 pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff; 109 pcix->powbear2 = 0x00000000; 110 pcix->powar2 = (POWAR_EN | POWAR_IO_READ | 111 POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1)); 112 113 pcix->pitar1 = 0x00000000; 114 pcix->piwbar1 = 0x00000000; 115 pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | 116 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); 117 118 pcix->powar3 = 0; 119 pcix->powar4 = 0; 120 pcix->piwar2 = 0; 121 pcix->piwar3 = 0; 122 123 pci_set_region(hose->regions + 0, 124 CONFIG_SYS_PCI1_MEM_BUS, 125 CONFIG_SYS_PCI1_MEM_PHYS, 126 CONFIG_SYS_PCI1_MEM_SIZE, 127 PCI_REGION_MEM); 128 129 pci_set_region(hose->regions + 1, 130 CONFIG_SYS_PCI1_IO_BUS, 131 CONFIG_SYS_PCI1_IO_PHYS, 132 CONFIG_SYS_PCI1_IO_SIZE, 133 PCI_REGION_IO); 134 135 hose->region_count = 2; 136 137 pci_register_hose(hose); 138 139 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) 140 /* 141 * This is a SW workaround for an apparent HW problem 142 * in the PCI controller on the MPC85555/41 CDS boards. 143 * The first config cycle must be to a valid, known 144 * device on the PCI bus in order to trick the PCI 145 * controller state machine into a known valid state. 146 * Without this, the first config cycle has the chance 147 * of hanging the controller permanently, just leaving 148 * it in a semi-working state, or leaving it working. 149 * 150 * Pick on the Tundra, Device 17, to get it right. 151 */ 152 { 153 u8 header_type; 154 155 pci_hose_read_config_byte(hose, 156 PCI_BDF(0,BRIDGE_ID,0), 157 PCI_HEADER_TYPE, 158 &header_type); 159 } 160 #endif 161 162 hose->last_busno = pci_hose_scan(hose); 163 164 #ifdef CONFIG_MPC85XX_PCI2 165 hose = &pci_hose[1]; 166 167 hose->first_busno = pci_hose[0].last_busno + 1; 168 hose->last_busno = 0xff; 169 170 pci_setup_indirect(hose, 171 (CONFIG_SYS_IMMR+0x9000), 172 (CONFIG_SYS_IMMR+0x9004)); 173 174 dev = PCI_BDF(hose->first_busno, 0, 0); 175 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 176 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 177 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 178 179 /* 180 * Clear non-reserved bits in status register. 181 */ 182 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 183 184 pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff; 185 pcix2->potear1 = 0x00000000; 186 pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff; 187 pcix2->powbear1 = 0x00000000; 188 pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | 189 POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1)); 190 191 pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff; 192 pcix2->potear2 = 0x00000000; 193 pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff; 194 pcix2->powbear2 = 0x00000000; 195 pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | 196 POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1)); 197 198 pcix2->pitar1 = 0x00000000; 199 pcix2->piwbar1 = 0x00000000; 200 pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | 201 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); 202 203 pcix2->powar3 = 0; 204 pcix2->powar4 = 0; 205 pcix2->piwar2 = 0; 206 pcix2->piwar3 = 0; 207 208 pci_set_region(hose->regions + 0, 209 CONFIG_SYS_PCI2_MEM_BUS, 210 CONFIG_SYS_PCI2_MEM_PHYS, 211 CONFIG_SYS_PCI2_MEM_SIZE, 212 PCI_REGION_MEM); 213 214 pci_set_region(hose->regions + 1, 215 CONFIG_SYS_PCI2_IO_BUS, 216 CONFIG_SYS_PCI2_IO_PHYS, 217 CONFIG_SYS_PCI2_IO_SIZE, 218 PCI_REGION_IO); 219 220 hose->region_count = 2; 221 222 /* 223 * Hose scan. 224 */ 225 pci_register_hose(hose); 226 227 hose->last_busno = pci_hose_scan(hose); 228 #endif 229 } 230 #endif /* !CONFIG_FSL_PCI_INIT */ 231