1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include "fsl_corenet_serdes.h" 28 29 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { 30 [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, 31 PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, 32 SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, 33 [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, 34 PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, 35 SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, 36 [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, 37 PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, 38 SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, 39 [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, 40 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, 41 NONE, NONE, SATA1, SATA2, }, 42 [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, 43 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 44 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, 45 [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, 46 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 47 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, 48 XAUI_FM1, XAUI_FM1, }, 49 [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, 50 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, 51 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, 52 SGMII_FM1_DTSEC4, }, 53 [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, 54 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, 55 NONE, NONE, SATA1, SATA2, }, 56 [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, 57 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 58 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, 59 SRIO1, }, 60 [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, 61 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 62 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, 63 [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, 64 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 65 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, 66 NONE, NONE, }, 67 [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, 68 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, 69 NONE, NONE, SATA1, SATA2, }, 70 [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, 71 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, 72 SATA1, SATA2, }, 73 [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, 74 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 75 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, 76 XAUI_FM1, XAUI_FM1, }, 77 [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, 78 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, 79 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, 80 SGMII_FM1_DTSEC4, }, 81 [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, 82 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, 83 NONE, NONE, SATA1, SATA2, }, 84 [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, 85 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 86 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, 87 [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, 88 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 89 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, 90 NONE, NONE, }, 91 [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, 92 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 93 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, 94 [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, 95 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 96 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, 97 NONE, NONE, }, 98 [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, 99 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 100 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, 101 XAUI_FM1, XAUI_FM1, }, 102 [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, 103 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, 104 NONE, NONE, SATA1, SATA2, }, 105 [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, 106 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, 107 NONE, NONE, SATA1, SATA2, }, 108 [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, 109 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 110 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, 111 NONE, NONE, }, 112 [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, 113 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, 114 NONE, NONE, SATA1, SATA2, }, 115 [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, 116 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, 117 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, 118 NONE, SATA1, SATA2, }, 119 [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, 120 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, 121 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, 122 [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, 123 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, 124 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, 125 NONE, SATA1, SATA2, }, 126 [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, 127 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, 128 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, 129 }; 130 131 enum srds_prtcl serdes_get_prtcl(int cfg, int lane) 132 { 133 if (!serdes_lane_enabled(lane)) 134 return NONE; 135 136 return serdes_cfg_tbl[cfg][lane]; 137 } 138 139 int is_serdes_prtcl_valid(u32 prtcl) { 140 int i; 141 142 if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) 143 return 0; 144 145 for (i = 0; i < SRDS_MAX_LANES; i++) { 146 if (serdes_cfg_tbl[prtcl][i] != NONE) 147 return 1; 148 } 149 150 return 0; 151 } 152