1 /* 2 * Copyright 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/fsl_serdes.h> 26 #include <asm/processor.h> 27 #include <asm/io.h> 28 #include "fsl_corenet_serdes.h" 29 30 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { 31 [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, 32 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, 33 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, 34 [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, 35 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, 36 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, 37 [0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, 38 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, 39 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, 40 [0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3, 41 SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, 42 XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, 43 [0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3, 44 SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, 45 XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, 46 [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 47 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, 48 XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE}, 49 [0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1, 50 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, 51 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, 52 NONE, NONE, NONE, NONE}, 53 [0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, 54 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, 55 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, 56 [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, 57 AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, 58 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1, 59 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}, 60 [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, 61 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1, 62 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}, 63 [0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1, 64 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, 65 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, 66 [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, 67 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, 68 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, 69 [0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, 70 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, 71 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, 72 }; 73 74 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 75 uint16_t srds_lpd_b[SRDS_MAX_BANK]; 76 #endif 77 78 enum srds_prtcl serdes_get_prtcl(int cfg, int lane) 79 { 80 if (!serdes_lane_enabled(lane)) 81 return NONE; 82 83 return serdes_cfg_tbl[cfg][lane]; 84 } 85 86 int is_serdes_prtcl_valid(u32 prtcl) { 87 int i; 88 89 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) 90 return 0; 91 92 for (i = 0; i < SRDS_MAX_LANES; i++) { 93 if (serdes_cfg_tbl[prtcl][i] != NONE) 94 return 1; 95 } 96 97 return 0; 98 } 99