1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/fsl_serdes.h> 9 #include <asm/processor.h> 10 #include <asm/io.h> 11 #include "fsl_corenet_serdes.h" 12 13 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { 14 [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, 15 NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 16 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, 17 [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, 18 NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 19 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, 20 [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 21 PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, 22 SATA2, NONE, NONE, NONE, NONE, }, 23 [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 24 PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1, 25 XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, }, 26 [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 27 PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, 28 PCIE3, NONE, NONE, NONE, NONE, }, 29 [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, 30 SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5, 31 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, 32 [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 33 PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA, 34 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, 35 NONE, NONE, NONE, }, 36 [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, 37 SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, 38 NONE, NONE, NONE, }, 39 [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, 40 SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1, 41 XAUI_FM1, NONE, NONE, NONE, NONE, }, 42 [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 43 PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, 44 NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, 45 [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, 46 SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, 47 NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, 48 [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, 49 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA, 50 SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, }, 51 }; 52 53 enum srds_prtcl serdes_get_prtcl(int cfg, int lane) 54 { 55 enum srds_prtcl prtcl; 56 u32 svr = get_svr(); 57 u32 ver = SVR_SOC_VER(svr); 58 59 if (!serdes_lane_enabled(lane)) 60 return NONE; 61 62 prtcl = serdes_cfg_tbl[cfg][lane]; 63 64 /* P2040[e] does not support XAUI */ 65 if (ver == SVR_P2040 && prtcl == XAUI_FM1) 66 prtcl = NONE; 67 68 return prtcl; 69 } 70 71 int is_serdes_prtcl_valid(u32 prtcl) 72 { 73 int i; 74 u32 svr = get_svr(); 75 u32 ver = SVR_SOC_VER(svr); 76 77 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) 78 return 0; 79 80 /* P2040[e] does not support XAUI */ 81 if (ver == SVR_P2040 && prtcl == XAUI_FM1) 82 return 0; 83 84 for (i = 0; i < SRDS_MAX_LANES; i++) { 85 if (serdes_cfg_tbl[prtcl][i] != NONE) 86 return 1; 87 } 88 89 return 0; 90 } 91