1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include "fsl_corenet_serdes.h" 28 29 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { 30 [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, 31 NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 32 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, 33 [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, 34 NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 35 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, 36 [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 37 PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, 38 SATA2, NONE, NONE, NONE, NONE, }, 39 [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 40 PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1, 41 XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, }, 42 [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 43 PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, 44 PCIE3, NONE, NONE, NONE, NONE, }, 45 [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, 46 SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5, 47 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, 48 [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 49 PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA, 50 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, 51 NONE, NONE, NONE, }, 52 [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, 53 SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, 54 NONE, NONE, NONE, }, 55 [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, 56 SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1, 57 XAUI_FM1, NONE, NONE, NONE, NONE, }, 58 [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, 59 PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, 60 NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, 61 [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, 62 SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, 63 NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, 64 [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, 65 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA, 66 SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, }, 67 }; 68 69 enum srds_prtcl serdes_get_prtcl(int cfg, int lane) 70 { 71 enum srds_prtcl prtcl; 72 u32 svr = get_svr(); 73 u32 ver = SVR_SOC_VER(svr); 74 75 if (!serdes_lane_enabled(lane)) 76 return NONE; 77 78 prtcl = serdes_cfg_tbl[cfg][lane]; 79 80 /* P2040[e] does not support XAUI */ 81 if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) 82 prtcl = NONE; 83 84 return prtcl; 85 } 86 87 int is_serdes_prtcl_valid(u32 prtcl) 88 { 89 int i; 90 u32 svr = get_svr(); 91 u32 ver = SVR_SOC_VER(svr); 92 93 if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) 94 return 0; 95 96 /* P2040[e] does not support XAUI */ 97 if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) 98 return 0; 99 100 for (i = 0; i < SRDS_MAX_LANES; i++) { 101 if (serdes_cfg_tbl[prtcl][i] != NONE) 102 return 1; 103 } 104 105 return 0; 106 } 107