1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <asm/fsl_serdes.h>
8 #include <asm/processor.h>
9 #include <asm/io.h>
10 #include "fsl_corenet_serdes.h"
11 
12 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
13 	[0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
14 		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
15 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
16 	[0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
17 		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
18 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
19 	[0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
20 		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
21 		SATA2, NONE, NONE, NONE, NONE, },
22 	[0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
23 		PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1,
24 		XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, },
25 	[0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
26 		PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
27 		PCIE3, NONE, NONE, NONE, NONE, },
28 	[0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
29 		SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
30 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
31 	[0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
32 		PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
33 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
34 		NONE, NONE, NONE, },
35 	[0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
36 		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
37 		NONE, NONE, NONE, },
38 	[0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
39 		SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1,
40 		XAUI_FM1, NONE, NONE, NONE, NONE, },
41 	[0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
42 		PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
43 		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
44 	[0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
45 		SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
46 		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
47 	[0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
48 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
49 		SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
50 };
51 
52 enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
53 {
54 	enum srds_prtcl prtcl;
55 	u32 svr = get_svr();
56 	u32 ver = SVR_SOC_VER(svr);
57 
58 	if (!serdes_lane_enabled(lane))
59 		return NONE;
60 
61 	prtcl = serdes_cfg_tbl[cfg][lane];
62 
63 	/* P2040[e] does not support XAUI */
64 	if (ver == SVR_P2040 && prtcl == XAUI_FM1)
65 		prtcl = NONE;
66 
67 	return prtcl;
68 }
69 
70 int is_serdes_prtcl_valid(u32 prtcl)
71 {
72 	int i;
73 	u32 svr = get_svr();
74 	u32 ver = SVR_SOC_VER(svr);
75 
76 	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
77 		return 0;
78 
79 	/* P2040[e] does not support XAUI */
80 	if (ver == SVR_P2040 && prtcl == XAUI_FM1)
81 		return 0;
82 
83 	for (i = 0; i < SRDS_MAX_LANES; i++) {
84 		if (serdes_cfg_tbl[prtcl][i] != NONE)
85 			return 1;
86 	}
87 
88 	return 0;
89 }
90