1 /*
2  * Copyright 2010 Freescale Semiconductor, Inc.
3  * Author: Timur Tabi <timur@freescale.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <config.h>
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/immap_85xx.h>
12 #include <asm/fsl_serdes.h>
13 
14 #define SRDS1_MAX_LANES		4
15 #define SRDS2_MAX_LANES		2
16 
17 static u32 serdes1_prtcl_map, serdes2_prtcl_map;
18 
19 static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
20 	[0x00] = {NONE, NONE, NONE, NONE},
21 	[0x01] = {NONE, NONE, NONE, NONE},
22 	[0x02] = {NONE, NONE, NONE, NONE},
23 	[0x03] = {NONE, NONE, NONE, NONE},
24 	[0x04] = {NONE, NONE, NONE, NONE},
25 	[0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
26 	[0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
27 	[0x09] = {PCIE1, NONE, NONE, NONE},
28 	[0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
29 	[0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
30 	[0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
31 	[0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
32 	[0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
33 	[0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
34 	[0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
35 	[0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
36 	[0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
37 	[0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
38 	[0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
39 	[0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
40 	[0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
41 	[0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
42 	[0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
43 	[0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
44 };
45 
46 static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
47 	[0x00] = {PCIE3, PCIE3},
48 	[0x01] = {PCIE2, PCIE3},
49 	[0x02] = {SATA1, SATA2},
50 	[0x03] = {SGMII_TSEC1, SGMII_TSEC2},
51 	[0x04] = {NONE, NONE},
52 	[0x06] = {SATA1, SATA2},
53 	[0x07] = {NONE, NONE},
54 	[0x09] = {PCIE3, PCIE2},
55 	[0x0a] = {SATA1, SATA2},
56 	[0x0b] = {NONE, NONE},
57 	[0x0d] = {PCIE3, PCIE2},
58 	[0x0e] = {SATA1, SATA2},
59 	[0x0f] = {NONE, NONE},
60 	[0x15] = {SGMII_TSEC1, SGMII_TSEC2},
61 	[0x16] = {SATA1, SATA2},
62 	[0x17] = {NONE, NONE},
63 	[0x18] = {PCIE3, PCIE3},
64 	[0x19] = {SGMII_TSEC1, SGMII_TSEC2},
65 	[0x1a] = {SATA1, SATA2},
66 	[0x1b] = {NONE, NONE},
67 	[0x1c] = {PCIE3, PCIE3},
68 	[0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
69 	[0x1e] = {SATA1, SATA2},
70 	[0x1f] = {NONE, NONE},
71 };
72 
73 int is_serdes_configured(enum srds_prtcl device)
74 {
75 	int ret = (1 << device) & serdes1_prtcl_map;
76 
77 	if (ret)
78 		return ret;
79 
80 	return (1 << device) & serdes2_prtcl_map;
81 }
82 
83 void fsl_serdes_init(void)
84 {
85 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
86 	u32 pordevsr = in_be32(&gur->pordevsr);
87 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
88 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
89 	int lane;
90 
91 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
92 
93 	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
94 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
95 		return;
96 	}
97 	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
98 		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
99 		serdes1_prtcl_map |= (1 << lane_prtcl);
100 	}
101 
102 	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
103 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
104 		return;
105 	}
106 
107 	for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
108 		enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
109 		serdes2_prtcl_map |= (1 << lane_prtcl);
110 	}
111 }
112