1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <config.h> 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/immap_85xx.h> 27 #include <asm/fsl_serdes.h> 28 29 typedef struct serdes_85xx { 30 u32 srdscr0; /* 0x00 - SRDS Control Register 0 */ 31 u32 srdscr1; /* 0x04 - SRDS Control Register 1 */ 32 u32 srdscr2; /* 0x08 - SRDS Control Register 2 */ 33 u32 srdscr3; /* 0x0C - SRDS Control Register 3 */ 34 u32 srdscr4; /* 0x10 - SRDS Control Register 4 */ 35 } serdes_85xx_t; 36 #define FSL_SRDSCR3_EIC0(x) (((x) & 0x1f) << 8) 37 #define FSL_SRDSCR3_EIC0_MASK FSL_SRDSCR3_EIC0(0x1f) 38 #define FSL_SRDSCR3_EIC1(x) (((x) & 0x1f) << 0) 39 #define FSL_SRDSCR3_EIC1_MASK FSL_SRDSCR3_EIC1(0x1f) 40 #define FSL_SRDSCR4_EIC2(x) (((x) & 0x1f) << 8) 41 #define FSL_SRDSCR4_EIC2_MASK FSL_SRDSCR4_EIC2(0x1f) 42 #define FSL_SRDSCR4_EIC3(x) (((x) & 0x1f) << 0) 43 #define FSL_SRDSCR4_EIC3_MASK FSL_SRDSCR4_EIC3(0x1f) 44 #define EIC_PCIE 0x13 45 #define EIC_SGMII 0x04 46 47 #define SRDS1_MAX_LANES 4 48 49 static u32 serdes1_prtcl_map; 50 51 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { 52 [0x0] = {PCIE1, NONE, NONE, NONE}, 53 [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, 54 [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, 55 [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3}, 56 }; 57 58 int is_serdes_configured(enum srds_prtcl prtcl) 59 { 60 return (1 << prtcl) & serdes1_prtcl_map; 61 } 62 63 void fsl_serdes_init(void) 64 { 65 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 66 serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR; 67 68 u32 pordevsr = in_be32(&gur->pordevsr); 69 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 70 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 71 int lane; 72 u32 mask, val; 73 74 debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); 75 76 if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { 77 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); 78 return; 79 } 80 81 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { 82 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; 83 serdes1_prtcl_map |= (1 << lane_prtcl); 84 } 85 86 /* Init SERDES Receiver electrical idle detection control for PCIe */ 87 88 /* Lane 0 is always PCIe 1 */ 89 mask = FSL_SRDSCR3_EIC0_MASK; 90 val = FSL_SRDSCR3_EIC0(EIC_PCIE); 91 92 /* Lane 1 */ 93 if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) || 94 (serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) { 95 mask |= FSL_SRDSCR3_EIC1_MASK; 96 val |= FSL_SRDSCR3_EIC1(EIC_PCIE); 97 } 98 99 /* Handle lanes 0 & 1 */ 100 clrsetbits_be32(&serdes->srdscr3, mask, val); 101 102 /* Handle lanes 2 & 3 */ 103 if (srds_cfg == 0x6) { 104 mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK; 105 val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE); 106 clrsetbits_be32(&serdes->srdscr4, mask, val); 107 } 108 109 /* 100 ms delay */ 110 udelay(100000); 111 } 112