1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <config.h>
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/immap_85xx.h>
11 #include <asm/fsl_serdes.h>
12 
13 typedef struct serdes_85xx {
14 	u32	srdscr0;	/* 0x00 - SRDS Control Register 0 */
15 	u32	srdscr1;	/* 0x04 - SRDS Control Register 1 */
16 	u32	srdscr2;	/* 0x08 - SRDS Control Register 2 */
17 	u32	srdscr3;	/* 0x0C - SRDS Control Register 3 */
18 	u32	srdscr4;	/* 0x10 - SRDS Control Register 4 */
19 } serdes_85xx_t;
20 #define FSL_SRDSCR3_EIC0(x)	(((x) & 0x1f) << 8)
21 #define FSL_SRDSCR3_EIC0_MASK	FSL_SRDSCR3_EIC0(0x1f)
22 #define FSL_SRDSCR3_EIC1(x)	(((x) & 0x1f) << 0)
23 #define FSL_SRDSCR3_EIC1_MASK	FSL_SRDSCR3_EIC1(0x1f)
24 #define FSL_SRDSCR4_EIC2(x)	(((x) & 0x1f) << 8)
25 #define FSL_SRDSCR4_EIC2_MASK	FSL_SRDSCR4_EIC2(0x1f)
26 #define FSL_SRDSCR4_EIC3(x)	(((x) & 0x1f) << 0)
27 #define FSL_SRDSCR4_EIC3_MASK	FSL_SRDSCR4_EIC3(0x1f)
28 #define EIC_PCIE	0x13
29 #define EIC_SGMII	0x04
30 
31 #define SRDS1_MAX_LANES		4
32 
33 static u32 serdes1_prtcl_map;
34 
35 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
36 	[0x0] = {PCIE1, NONE, NONE, NONE},
37 	[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
38 	[0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
39 	[0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
40 };
41 
42 int is_serdes_configured(enum srds_prtcl prtcl)
43 {
44 	return (1 << prtcl) & serdes1_prtcl_map;
45 }
46 
47 void fsl_serdes_init(void)
48 {
49 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 	serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
51 
52 	u32 pordevsr = in_be32(&gur->pordevsr);
53 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
54 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
55 	int lane;
56 	u32 mask, val;
57 
58 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
59 
60 	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
61 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
62 		return;
63 	}
64 
65 	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
66 		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
67 		serdes1_prtcl_map |= (1 << lane_prtcl);
68 	}
69 
70 	/* Init SERDES Receiver electrical idle detection control for PCIe */
71 
72 	/* Lane 0 is always PCIe 1 */
73 	mask = FSL_SRDSCR3_EIC0_MASK;
74 	val = FSL_SRDSCR3_EIC0(EIC_PCIE);
75 
76 	/* Lane 1 */
77 	if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) ||
78 	    (serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) {
79 		mask |= FSL_SRDSCR3_EIC1_MASK;
80 		val |= FSL_SRDSCR3_EIC1(EIC_PCIE);
81 	}
82 
83 	/* Handle lanes 0 & 1 */
84 	clrsetbits_be32(&serdes->srdscr3, mask, val);
85 
86 	/* Handle lanes 2 & 3 */
87 	if (srds_cfg == 0x6) {
88 		mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK;
89 		val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE);
90 		clrsetbits_be32(&serdes->srdscr4, mask, val);
91 	}
92 
93 	/* 100 ms delay */
94 	udelay(100000);
95 }
96