1 /*
2  * Copyright 2010 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <config.h>
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/immap_85xx.h>
11 #include <asm/fsl_serdes.h>
12 
13 #define SRDS1_MAX_LANES		4
14 
15 static u32 serdes1_prtcl_map;
16 
17 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
18 	[0x0] = {PCIE1, NONE, NONE, NONE},
19 	[0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
20 	[0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
21 	[0x3] = {SRIO1, SRIO2, NONE, NONE},
22 	[0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2},
23 	[0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
24 	[0x6] = {PCIE1, NONE, SRIO1, SRIO2},
25 	[0x7] = {PCIE1, PCIE1, SRIO1, SRIO2},
26 	[0x8] = {PCIE1, PCIE1, SRIO1, SRIO2},
27 	[0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
28 	[0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
29 	[0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
30 	[0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2},
31 	[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
32 };
33 
34 int is_serdes_configured(enum srds_prtcl prtcl)
35 {
36 	return (1 << prtcl) & serdes1_prtcl_map;
37 }
38 
39 void fsl_serdes_init(void)
40 {
41 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
42 	u32 pordevsr = in_be32(&gur->pordevsr);
43 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
44 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
45 	int lane;
46 
47 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
48 
49 	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
50 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
51 		return;
52 	}
53 
54 	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
55 		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
56 		serdes1_prtcl_map |= (1 << lane_prtcl);
57 	}
58 }
59