1 /*
2  * Copyright 2010 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <config.h>
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/immap_85xx.h>
11 #include <asm/fsl_serdes.h>
12 
13 #define SRDS1_MAX_LANES		8
14 #define SRDS2_MAX_LANES		4
15 
16 static u32 serdes1_prtcl_map, serdes2_prtcl_map;
17 
18 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
19 	[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
20 	[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
21 	[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
22 	[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
23 	[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
24 	[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
25 };
26 
27 static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
28 	[0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
29 	[0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
30 	[0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
31 	[0x6] = {PCIE3, NONE, NONE, NONE},
32 	[0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3},
33 };
34 
35 int is_serdes_configured(enum srds_prtcl device)
36 {
37 	int ret = (1 << device) & serdes1_prtcl_map;
38 
39 	if (ret)
40 		return ret;
41 
42 	return (1 << device) & serdes2_prtcl_map;
43 }
44 
45 void fsl_serdes_init(void)
46 {
47 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
48 	u32 pordevsr = in_be32(&gur->pordevsr);
49 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
50 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
51 	int lane;
52 
53 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
54 
55 	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
56 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
57 		return;
58 	}
59 	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
60 		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
61 		serdes1_prtcl_map |= (1 << lane_prtcl);
62 	}
63 
64 	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
65 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
66 		return;
67 	}
68 
69 	for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
70 		enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
71 		serdes2_prtcl_map |= (1 << lane_prtcl);
72 	}
73 
74 	if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
75 		serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);
76 
77 	if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
78 		serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
79 }
80