1 /* 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/processor.h> 25 #include <ioports.h> 26 #include <lmb.h> 27 #include <asm/io.h> 28 #include <asm/mmu.h> 29 #include <asm/fsl_law.h> 30 #include "mp.h" 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 u32 get_my_id() 35 { 36 return mfspr(SPRN_PIR); 37 } 38 39 int cpu_reset(int nr) 40 { 41 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 42 out_be32(&pic->pir, 1 << nr); 43 /* the dummy read works around an errata on early 85xx MP PICs */ 44 (void)in_be32(&pic->pir); 45 out_be32(&pic->pir, 0x0); 46 47 return 0; 48 } 49 50 int cpu_status(int nr) 51 { 52 u32 *table, id = get_my_id(); 53 54 if (nr == id) { 55 table = (u32 *)get_spin_virt_addr(); 56 printf("table base @ 0x%p\n", table); 57 } else { 58 table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; 59 printf("Running on cpu %d\n", id); 60 printf("\n"); 61 printf("table @ 0x%p\n", table); 62 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); 63 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); 64 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); 65 printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]); 66 } 67 68 return 0; 69 } 70 71 #ifdef CONFIG_FSL_CORENET 72 int cpu_disable(int nr) 73 { 74 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 75 76 setbits_be32(&gur->coredisrl, 1 << nr); 77 78 return 0; 79 } 80 81 int is_core_disabled(int nr) { 82 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 83 u32 coredisrl = in_be32(&gur->coredisrl); 84 85 return (coredisrl & (1 << nr)); 86 } 87 #else 88 int cpu_disable(int nr) 89 { 90 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 91 92 switch (nr) { 93 case 0: 94 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); 95 break; 96 case 1: 97 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); 98 break; 99 default: 100 printf("Invalid cpu number for disable %d\n", nr); 101 return 1; 102 } 103 104 return 0; 105 } 106 107 int is_core_disabled(int nr) { 108 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 109 u32 devdisr = in_be32(&gur->devdisr); 110 111 switch (nr) { 112 case 0: 113 return (devdisr & MPC85xx_DEVDISR_CPU0); 114 case 1: 115 return (devdisr & MPC85xx_DEVDISR_CPU1); 116 default: 117 printf("Invalid cpu number for disable %d\n", nr); 118 } 119 120 return 0; 121 } 122 #endif 123 124 static u8 boot_entry_map[4] = { 125 0, 126 BOOT_ENTRY_PIR, 127 BOOT_ENTRY_R3_LOWER, 128 BOOT_ENTRY_R6_LOWER, 129 }; 130 131 int cpu_release(int nr, int argc, char * const argv[]) 132 { 133 u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; 134 u64 boot_addr; 135 136 if (nr == get_my_id()) { 137 printf("Invalid to release the boot core.\n\n"); 138 return 1; 139 } 140 141 if (argc != 4) { 142 printf("Invalid number of arguments to release.\n\n"); 143 return 1; 144 } 145 146 boot_addr = simple_strtoull(argv[0], NULL, 16); 147 148 /* handle pir, r3, r6 */ 149 for (i = 1; i < 4; i++) { 150 if (argv[i][0] != '-') { 151 u8 entry = boot_entry_map[i]; 152 val = simple_strtoul(argv[i], NULL, 16); 153 table[entry] = val; 154 } 155 } 156 157 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); 158 159 /* ensure all table updates complete before final address write */ 160 eieio(); 161 162 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); 163 164 return 0; 165 } 166 167 u32 determine_mp_bootpg(void) 168 { 169 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ 170 if ((u64)gd->ram_size > 0xfffff000) 171 return (0xfffff000); 172 173 return (gd->ram_size - 4096); 174 } 175 176 ulong get_spin_phys_addr(void) 177 { 178 extern ulong __secondary_start_page; 179 extern ulong __spin_table; 180 181 return (determine_mp_bootpg() + 182 (ulong)&__spin_table - (ulong)&__secondary_start_page); 183 } 184 185 ulong get_spin_virt_addr(void) 186 { 187 extern ulong __secondary_start_page; 188 extern ulong __spin_table; 189 190 return (CONFIG_BPTR_VIRT_ADDR + 191 (ulong)&__spin_table - (ulong)&__secondary_start_page); 192 } 193 194 #ifdef CONFIG_FSL_CORENET 195 static void plat_mp_up(unsigned long bootpg) 196 { 197 u32 up, cpu_up_mask, whoami; 198 u32 *table = (u32 *)get_spin_virt_addr(); 199 volatile ccsr_gur_t *gur; 200 volatile ccsr_local_t *ccm; 201 volatile ccsr_rcpm_t *rcpm; 202 volatile ccsr_pic_t *pic; 203 int timeout = 10; 204 u32 nr_cpus; 205 struct law_entry e; 206 207 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 208 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); 209 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 210 pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 211 212 nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; 213 214 whoami = in_be32(&pic->whoami); 215 cpu_up_mask = 1 << whoami; 216 out_be32(&ccm->bstrl, bootpg); 217 218 e = find_law(bootpg); 219 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K); 220 221 /* readback to sync write */ 222 in_be32(&ccm->bstrar); 223 224 /* disable time base at the platform */ 225 out_be32(&rcpm->ctbenrl, cpu_up_mask); 226 227 /* release the hounds */ 228 up = ((1 << nr_cpus) - 1); 229 out_be32(&gur->brrl, up); 230 231 /* wait for everyone */ 232 while (timeout) { 233 int i; 234 for (i = 0; i < nr_cpus; i++) { 235 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 236 cpu_up_mask |= (1 << i); 237 }; 238 239 if ((cpu_up_mask & up) == up) 240 break; 241 242 udelay(100); 243 timeout--; 244 } 245 246 if (timeout == 0) 247 printf("CPU up timeout. CPU up mask is %x should be %x\n", 248 cpu_up_mask, up); 249 250 /* enable time base at the platform */ 251 out_be32(&rcpm->ctbenrl, 0); 252 mtspr(SPRN_TBWU, 0); 253 mtspr(SPRN_TBWL, 0); 254 out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1); 255 256 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 257 /* 258 * Disabling Boot Page Translation allows the memory region 0xfffff000 259 * to 0xffffffff to be used normally. Leaving Boot Page Translation 260 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 261 * unusable for normal operation but it does allow OSes to easily 262 * reset a processor core to put it back into U-Boot's spinloop. 263 */ 264 clrbits_be32(&ecm->bptr, 0x80000000); 265 #endif 266 } 267 #else 268 static void plat_mp_up(unsigned long bootpg) 269 { 270 u32 up, cpu_up_mask, whoami; 271 u32 *table = (u32 *)get_spin_virt_addr(); 272 volatile u32 bpcr; 273 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 274 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 275 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 276 u32 devdisr; 277 int timeout = 10; 278 279 whoami = in_be32(&pic->whoami); 280 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); 281 282 /* disable time base at the platform */ 283 devdisr = in_be32(&gur->devdisr); 284 if (whoami) 285 devdisr |= MPC85xx_DEVDISR_TB0; 286 else 287 devdisr |= MPC85xx_DEVDISR_TB1; 288 out_be32(&gur->devdisr, devdisr); 289 290 /* release the hounds */ 291 up = ((1 << cpu_numcores()) - 1); 292 bpcr = in_be32(&ecm->eebpcr); 293 bpcr |= (up << 24); 294 out_be32(&ecm->eebpcr, bpcr); 295 asm("sync; isync; msync"); 296 297 cpu_up_mask = 1 << whoami; 298 /* wait for everyone */ 299 while (timeout) { 300 int i; 301 for (i = 0; i < cpu_numcores(); i++) { 302 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 303 cpu_up_mask |= (1 << i); 304 }; 305 306 if ((cpu_up_mask & up) == up) 307 break; 308 309 udelay(100); 310 timeout--; 311 } 312 313 if (timeout == 0) 314 printf("CPU up timeout. CPU up mask is %x should be %x\n", 315 cpu_up_mask, up); 316 317 /* enable time base at the platform */ 318 if (whoami) 319 devdisr |= MPC85xx_DEVDISR_TB1; 320 else 321 devdisr |= MPC85xx_DEVDISR_TB0; 322 out_be32(&gur->devdisr, devdisr); 323 mtspr(SPRN_TBWU, 0); 324 mtspr(SPRN_TBWL, 0); 325 326 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); 327 out_be32(&gur->devdisr, devdisr); 328 329 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 330 /* 331 * Disabling Boot Page Translation allows the memory region 0xfffff000 332 * to 0xffffffff to be used normally. Leaving Boot Page Translation 333 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 334 * unusable for normal operation but it does allow OSes to easily 335 * reset a processor core to put it back into U-Boot's spinloop. 336 */ 337 clrbits_be32(&ecm->bptr, 0x80000000); 338 #endif 339 } 340 #endif 341 342 void cpu_mp_lmb_reserve(struct lmb *lmb) 343 { 344 u32 bootpg = determine_mp_bootpg(); 345 346 lmb_reserve(lmb, bootpg, 4096); 347 } 348 349 void setup_mp(void) 350 { 351 extern ulong __secondary_start_page; 352 extern ulong __bootpg_addr; 353 ulong fixup = (ulong)&__secondary_start_page; 354 u32 bootpg = determine_mp_bootpg(); 355 356 /* Store the bootpg's SDRAM address for use by secondary CPU cores */ 357 __bootpg_addr = bootpg; 358 359 /* look for the tlb covering the reset page, there better be one */ 360 int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); 361 362 /* we found a match */ 363 if (i != -1) { 364 /* map reset page to bootpg so we can copy code there */ 365 disable_tlb(i); 366 367 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ 368 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 369 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ 370 371 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); 372 373 plat_mp_up(bootpg); 374 } else { 375 puts("WARNING: No reset page TLB. " 376 "Skipping secondary core setup\n"); 377 } 378 } 379