1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/processor.h> 25 #include <ioports.h> 26 #include <lmb.h> 27 #include <asm/io.h> 28 #include <asm/mmu.h> 29 #include <asm/fsl_law.h> 30 #include <asm/fsl_ddr_sdram.h> 31 #include "mp.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 u32 fsl_ddr_get_intl3r(void); 35 36 extern u32 __spin_table[]; 37 38 u32 get_my_id() 39 { 40 return mfspr(SPRN_PIR); 41 } 42 43 /* 44 * Determine if U-Boot should keep secondary cores in reset, or let them out 45 * of reset and hold them in a spinloop 46 */ 47 int hold_cores_in_reset(int verbose) 48 { 49 /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */ 50 if (getenv_yesno("mp_holdoff") == 1) { 51 if (verbose) { 52 puts("Secondary cores are being held in reset.\n"); 53 puts("See 'mp_holdoff' environment variable\n"); 54 } 55 56 return 1; 57 } 58 59 return 0; 60 } 61 62 int cpu_reset(int nr) 63 { 64 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 65 out_be32(&pic->pir, 1 << nr); 66 /* the dummy read works around an errata on early 85xx MP PICs */ 67 (void)in_be32(&pic->pir); 68 out_be32(&pic->pir, 0x0); 69 70 return 0; 71 } 72 73 int cpu_status(int nr) 74 { 75 u32 *table, id = get_my_id(); 76 77 if (hold_cores_in_reset(1)) 78 return 0; 79 80 if (nr == id) { 81 table = (u32 *)&__spin_table; 82 printf("table base @ 0x%p\n", table); 83 } else { 84 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; 85 printf("Running on cpu %d\n", id); 86 printf("\n"); 87 printf("table @ 0x%p\n", table); 88 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); 89 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); 90 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); 91 } 92 93 return 0; 94 } 95 96 #ifdef CONFIG_FSL_CORENET 97 int cpu_disable(int nr) 98 { 99 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 100 101 setbits_be32(&gur->coredisrl, 1 << nr); 102 103 return 0; 104 } 105 106 int is_core_disabled(int nr) { 107 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 108 u32 coredisrl = in_be32(&gur->coredisrl); 109 110 return (coredisrl & (1 << nr)); 111 } 112 #else 113 int cpu_disable(int nr) 114 { 115 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 116 117 switch (nr) { 118 case 0: 119 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); 120 break; 121 case 1: 122 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); 123 break; 124 default: 125 printf("Invalid cpu number for disable %d\n", nr); 126 return 1; 127 } 128 129 return 0; 130 } 131 132 int is_core_disabled(int nr) { 133 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 134 u32 devdisr = in_be32(&gur->devdisr); 135 136 switch (nr) { 137 case 0: 138 return (devdisr & MPC85xx_DEVDISR_CPU0); 139 case 1: 140 return (devdisr & MPC85xx_DEVDISR_CPU1); 141 default: 142 printf("Invalid cpu number for disable %d\n", nr); 143 } 144 145 return 0; 146 } 147 #endif 148 149 static u8 boot_entry_map[4] = { 150 0, 151 BOOT_ENTRY_PIR, 152 BOOT_ENTRY_R3_LOWER, 153 }; 154 155 int cpu_release(int nr, int argc, char * const argv[]) 156 { 157 u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; 158 u64 boot_addr; 159 160 if (hold_cores_in_reset(1)) 161 return 0; 162 163 if (nr == get_my_id()) { 164 printf("Invalid to release the boot core.\n\n"); 165 return 1; 166 } 167 168 if (argc != 4) { 169 printf("Invalid number of arguments to release.\n\n"); 170 return 1; 171 } 172 173 boot_addr = simple_strtoull(argv[0], NULL, 16); 174 175 /* handle pir, r3 */ 176 for (i = 1; i < 3; i++) { 177 if (argv[i][0] != '-') { 178 u8 entry = boot_entry_map[i]; 179 val = simple_strtoul(argv[i], NULL, 16); 180 table[entry] = val; 181 } 182 } 183 184 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); 185 186 /* ensure all table updates complete before final address write */ 187 eieio(); 188 189 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); 190 191 return 0; 192 } 193 194 u32 determine_mp_bootpg(unsigned int *pagesize) 195 { 196 u32 bootpg; 197 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 198 u32 svr = get_svr(); 199 u32 granule_size, check; 200 struct law_entry e; 201 #endif 202 203 204 /* use last 4K of mapped memory */ 205 bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? 206 CONFIG_MAX_MEM_MAPPED : gd->ram_size) + 207 CONFIG_SYS_SDRAM_BASE - 4096; 208 if (pagesize) 209 *pagesize = 4096; 210 211 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 212 /* 213 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240, 214 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But 215 * the way boot page chosen in u-boot avoids hitting this erratum. So only 216 * thw workaround for 3-way interleaving is needed. 217 * 218 * To make sure boot page translation works with 3-Way DDR interleaving 219 * enforce a check for the following constrains 220 * 8K granule size requires BRSIZE=8K and 221 * bootpg >> log2(BRSIZE) %3 == 1 222 * 4K and 1K granule size requires BRSIZE=4K and 223 * bootpg >> log2(BRSIZE) %3 == 0 224 */ 225 if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) { 226 e = find_law(bootpg); 227 switch (e.trgt_id) { 228 case LAW_TRGT_IF_DDR_INTLV_123: 229 granule_size = fsl_ddr_get_intl3r() & 0x1f; 230 if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) { 231 if (pagesize) 232 *pagesize = 8192; 233 bootpg &= 0xffffe000; /* align to 8KB */ 234 check = bootpg >> 13; 235 while ((check % 3) != 1) 236 check--; 237 bootpg = check << 13; 238 debug("Boot page (8K) at 0x%08x\n", bootpg); 239 break; 240 } else { 241 bootpg &= 0xfffff000; /* align to 4KB */ 242 check = bootpg >> 12; 243 while ((check % 3) != 0) 244 check--; 245 bootpg = check << 12; 246 debug("Boot page (4K) at 0x%08x\n", bootpg); 247 } 248 break; 249 default: 250 break; 251 } 252 } 253 #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */ 254 255 return bootpg; 256 } 257 258 phys_addr_t get_spin_phys_addr(void) 259 { 260 return virt_to_phys(&__spin_table); 261 } 262 263 #ifdef CONFIG_FSL_CORENET 264 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) 265 { 266 u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K; 267 u32 *table = (u32 *)&__spin_table; 268 volatile ccsr_gur_t *gur; 269 volatile ccsr_local_t *ccm; 270 volatile ccsr_rcpm_t *rcpm; 271 volatile ccsr_pic_t *pic; 272 int timeout = 10; 273 u32 mask = cpu_mask(); 274 struct law_entry e; 275 276 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 277 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); 278 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 279 pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 280 281 whoami = in_be32(&pic->whoami); 282 cpu_up_mask = 1 << whoami; 283 out_be32(&ccm->bstrl, bootpg); 284 285 e = find_law(bootpg); 286 /* pagesize is only 4K or 8K */ 287 if (pagesize == 8192) 288 brsize = LAW_SIZE_8K; 289 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize); 290 debug("BRSIZE is 0x%x\n", brsize); 291 292 /* readback to sync write */ 293 in_be32(&ccm->bstrar); 294 295 /* disable time base at the platform */ 296 out_be32(&rcpm->ctbenrl, cpu_up_mask); 297 298 out_be32(&gur->brrl, mask); 299 300 /* wait for everyone */ 301 while (timeout) { 302 unsigned int i, cpu, nr_cpus = cpu_numcores(); 303 304 for_each_cpu(i, cpu, nr_cpus, mask) { 305 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 306 cpu_up_mask |= (1 << cpu); 307 } 308 309 if ((cpu_up_mask & mask) == mask) 310 break; 311 312 udelay(100); 313 timeout--; 314 } 315 316 if (timeout == 0) 317 printf("CPU up timeout. CPU up mask is %x should be %x\n", 318 cpu_up_mask, mask); 319 320 /* enable time base at the platform */ 321 out_be32(&rcpm->ctbenrl, 0); 322 323 /* readback to sync write */ 324 in_be32(&rcpm->ctbenrl); 325 326 mtspr(SPRN_TBWU, 0); 327 mtspr(SPRN_TBWL, 0); 328 329 out_be32(&rcpm->ctbenrl, mask); 330 331 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 332 /* 333 * Disabling Boot Page Translation allows the memory region 0xfffff000 334 * to 0xffffffff to be used normally. Leaving Boot Page Translation 335 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 336 * unusable for normal operation but it does allow OSes to easily 337 * reset a processor core to put it back into U-Boot's spinloop. 338 */ 339 clrbits_be32(&ccm->bstrar, LAW_EN); 340 #endif 341 } 342 #else 343 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) 344 { 345 u32 up, cpu_up_mask, whoami; 346 u32 *table = (u32 *)&__spin_table; 347 volatile u32 bpcr; 348 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 349 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 350 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 351 u32 devdisr; 352 int timeout = 10; 353 354 whoami = in_be32(&pic->whoami); 355 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); 356 357 /* disable time base at the platform */ 358 devdisr = in_be32(&gur->devdisr); 359 if (whoami) 360 devdisr |= MPC85xx_DEVDISR_TB0; 361 else 362 devdisr |= MPC85xx_DEVDISR_TB1; 363 out_be32(&gur->devdisr, devdisr); 364 365 /* release the hounds */ 366 up = ((1 << cpu_numcores()) - 1); 367 bpcr = in_be32(&ecm->eebpcr); 368 bpcr |= (up << 24); 369 out_be32(&ecm->eebpcr, bpcr); 370 asm("sync; isync; msync"); 371 372 cpu_up_mask = 1 << whoami; 373 /* wait for everyone */ 374 while (timeout) { 375 int i; 376 for (i = 0; i < cpu_numcores(); i++) { 377 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 378 cpu_up_mask |= (1 << i); 379 }; 380 381 if ((cpu_up_mask & up) == up) 382 break; 383 384 udelay(100); 385 timeout--; 386 } 387 388 if (timeout == 0) 389 printf("CPU up timeout. CPU up mask is %x should be %x\n", 390 cpu_up_mask, up); 391 392 /* enable time base at the platform */ 393 if (whoami) 394 devdisr |= MPC85xx_DEVDISR_TB1; 395 else 396 devdisr |= MPC85xx_DEVDISR_TB0; 397 out_be32(&gur->devdisr, devdisr); 398 399 /* readback to sync write */ 400 in_be32(&gur->devdisr); 401 402 mtspr(SPRN_TBWU, 0); 403 mtspr(SPRN_TBWL, 0); 404 405 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); 406 out_be32(&gur->devdisr, devdisr); 407 408 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 409 /* 410 * Disabling Boot Page Translation allows the memory region 0xfffff000 411 * to 0xffffffff to be used normally. Leaving Boot Page Translation 412 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 413 * unusable for normal operation but it does allow OSes to easily 414 * reset a processor core to put it back into U-Boot's spinloop. 415 */ 416 clrbits_be32(&ecm->bptr, 0x80000000); 417 #endif 418 } 419 #endif 420 421 void cpu_mp_lmb_reserve(struct lmb *lmb) 422 { 423 u32 bootpg = determine_mp_bootpg(NULL); 424 425 lmb_reserve(lmb, bootpg, 4096); 426 } 427 428 void setup_mp(void) 429 { 430 extern u32 __secondary_start_page; 431 extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page; 432 433 int i; 434 ulong fixup = (u32)&__secondary_start_page; 435 u32 bootpg, bootpg_map, pagesize; 436 437 bootpg = determine_mp_bootpg(&pagesize); 438 439 /* 440 * pagesize is only 4K or 8K 441 * we only use the last 4K of boot page 442 * bootpg_map saves the address for the boot page 443 * 8K is used for the workaround of 3-way DDR interleaving 444 */ 445 446 bootpg_map = bootpg; 447 448 if (pagesize == 8192) 449 bootpg += 4096; /* use 2nd half */ 450 451 /* Some OSes expect secondary cores to be held in reset */ 452 if (hold_cores_in_reset(0)) 453 return; 454 455 /* 456 * Store the bootpg's cache-able half address for use by secondary 457 * CPU cores to continue to boot 458 */ 459 __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page); 460 461 /* Store spin table's physical address for use by secondary cores */ 462 __spin_table_addr = (u32)get_spin_phys_addr(); 463 464 /* flush bootpg it before copying invalidate any staled cacheline */ 465 flush_cache(bootpg, 4096); 466 467 /* look for the tlb covering the reset page, there better be one */ 468 i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); 469 470 /* we found a match */ 471 if (i != -1) { 472 /* map reset page to bootpg so we can copy code there */ 473 disable_tlb(i); 474 475 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ 476 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 477 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ 478 479 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); 480 481 plat_mp_up(bootpg_map, pagesize); 482 } else { 483 puts("WARNING: No reset page TLB. " 484 "Skipping secondary core setup\n"); 485 } 486 } 487