1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/processor.h> 25 #include <ioports.h> 26 #include <lmb.h> 27 #include <asm/io.h> 28 #include <asm/mmu.h> 29 #include <asm/fsl_law.h> 30 #include "mp.h" 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 u32 get_my_id() 35 { 36 return mfspr(SPRN_PIR); 37 } 38 39 /* 40 * Determine if U-Boot should keep secondary cores in reset, or let them out 41 * of reset and hold them in a spinloop 42 */ 43 int hold_cores_in_reset(int verbose) 44 { 45 const char *s = getenv("mp_holdoff"); 46 47 /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */ 48 if (s && (*s == 'y' || *s == 'Y' || *s == '1')) { 49 if (verbose) { 50 puts("Secondary cores are being held in reset.\n"); 51 puts("See 'mp_holdoff' environment variable\n"); 52 } 53 54 return 1; 55 } 56 57 return 0; 58 } 59 60 int cpu_reset(int nr) 61 { 62 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 63 out_be32(&pic->pir, 1 << nr); 64 /* the dummy read works around an errata on early 85xx MP PICs */ 65 (void)in_be32(&pic->pir); 66 out_be32(&pic->pir, 0x0); 67 68 return 0; 69 } 70 71 int cpu_status(int nr) 72 { 73 u32 *table, id = get_my_id(); 74 75 if (hold_cores_in_reset(1)) 76 return 0; 77 78 if (nr == id) { 79 table = (u32 *)get_spin_virt_addr(); 80 printf("table base @ 0x%p\n", table); 81 } else { 82 table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; 83 printf("Running on cpu %d\n", id); 84 printf("\n"); 85 printf("table @ 0x%p\n", table); 86 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); 87 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); 88 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); 89 printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]); 90 } 91 92 return 0; 93 } 94 95 #ifdef CONFIG_FSL_CORENET 96 int cpu_disable(int nr) 97 { 98 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 99 100 setbits_be32(&gur->coredisrl, 1 << nr); 101 102 return 0; 103 } 104 105 int is_core_disabled(int nr) { 106 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 107 u32 coredisrl = in_be32(&gur->coredisrl); 108 109 return (coredisrl & (1 << nr)); 110 } 111 #else 112 int cpu_disable(int nr) 113 { 114 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 115 116 switch (nr) { 117 case 0: 118 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); 119 break; 120 case 1: 121 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); 122 break; 123 default: 124 printf("Invalid cpu number for disable %d\n", nr); 125 return 1; 126 } 127 128 return 0; 129 } 130 131 int is_core_disabled(int nr) { 132 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 133 u32 devdisr = in_be32(&gur->devdisr); 134 135 switch (nr) { 136 case 0: 137 return (devdisr & MPC85xx_DEVDISR_CPU0); 138 case 1: 139 return (devdisr & MPC85xx_DEVDISR_CPU1); 140 default: 141 printf("Invalid cpu number for disable %d\n", nr); 142 } 143 144 return 0; 145 } 146 #endif 147 148 static u8 boot_entry_map[4] = { 149 0, 150 BOOT_ENTRY_PIR, 151 BOOT_ENTRY_R3_LOWER, 152 BOOT_ENTRY_R6_LOWER, 153 }; 154 155 int cpu_release(int nr, int argc, char * const argv[]) 156 { 157 u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; 158 u64 boot_addr; 159 160 if (hold_cores_in_reset(1)) 161 return 0; 162 163 if (nr == get_my_id()) { 164 printf("Invalid to release the boot core.\n\n"); 165 return 1; 166 } 167 168 if (argc != 4) { 169 printf("Invalid number of arguments to release.\n\n"); 170 return 1; 171 } 172 173 boot_addr = simple_strtoull(argv[0], NULL, 16); 174 175 /* handle pir, r3, r6 */ 176 for (i = 1; i < 4; i++) { 177 if (argv[i][0] != '-') { 178 u8 entry = boot_entry_map[i]; 179 val = simple_strtoul(argv[i], NULL, 16); 180 table[entry] = val; 181 } 182 } 183 184 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); 185 186 /* ensure all table updates complete before final address write */ 187 eieio(); 188 189 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); 190 191 return 0; 192 } 193 194 u32 determine_mp_bootpg(void) 195 { 196 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ 197 if ((u64)gd->ram_size > 0xfffff000) 198 return (0xfffff000); 199 200 return (gd->ram_size - 4096); 201 } 202 203 ulong get_spin_phys_addr(void) 204 { 205 extern ulong __secondary_start_page; 206 extern ulong __spin_table; 207 208 return (determine_mp_bootpg() + 209 (ulong)&__spin_table - (ulong)&__secondary_start_page); 210 } 211 212 ulong get_spin_virt_addr(void) 213 { 214 extern ulong __secondary_start_page; 215 extern ulong __spin_table; 216 217 return (CONFIG_BPTR_VIRT_ADDR + 218 (ulong)&__spin_table - (ulong)&__secondary_start_page); 219 } 220 221 #ifdef CONFIG_FSL_CORENET 222 static void plat_mp_up(unsigned long bootpg) 223 { 224 u32 cpu_up_mask, whoami; 225 u32 *table = (u32 *)get_spin_virt_addr(); 226 volatile ccsr_gur_t *gur; 227 volatile ccsr_local_t *ccm; 228 volatile ccsr_rcpm_t *rcpm; 229 volatile ccsr_pic_t *pic; 230 int timeout = 10; 231 u32 mask = cpu_mask(); 232 struct law_entry e; 233 234 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 235 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); 236 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 237 pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 238 239 whoami = in_be32(&pic->whoami); 240 cpu_up_mask = 1 << whoami; 241 out_be32(&ccm->bstrl, bootpg); 242 243 e = find_law(bootpg); 244 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K); 245 246 /* readback to sync write */ 247 in_be32(&ccm->bstrar); 248 249 /* disable time base at the platform */ 250 out_be32(&rcpm->ctbenrl, cpu_up_mask); 251 252 out_be32(&gur->brrl, mask); 253 254 /* wait for everyone */ 255 while (timeout) { 256 unsigned int i, cpu, nr_cpus = cpu_numcores(); 257 258 for_each_cpu(i, cpu, nr_cpus, mask) { 259 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 260 cpu_up_mask |= (1 << cpu); 261 } 262 263 if ((cpu_up_mask & mask) == mask) 264 break; 265 266 udelay(100); 267 timeout--; 268 } 269 270 if (timeout == 0) 271 printf("CPU up timeout. CPU up mask is %x should be %x\n", 272 cpu_up_mask, mask); 273 274 /* enable time base at the platform */ 275 out_be32(&rcpm->ctbenrl, 0); 276 277 /* readback to sync write */ 278 in_be32(&rcpm->ctbenrl); 279 280 mtspr(SPRN_TBWU, 0); 281 mtspr(SPRN_TBWL, 0); 282 283 out_be32(&rcpm->ctbenrl, mask); 284 285 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 286 /* 287 * Disabling Boot Page Translation allows the memory region 0xfffff000 288 * to 0xffffffff to be used normally. Leaving Boot Page Translation 289 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 290 * unusable for normal operation but it does allow OSes to easily 291 * reset a processor core to put it back into U-Boot's spinloop. 292 */ 293 clrbits_be32(&ccm->bstrar, LAW_EN); 294 #endif 295 } 296 #else 297 static void plat_mp_up(unsigned long bootpg) 298 { 299 u32 up, cpu_up_mask, whoami; 300 u32 *table = (u32 *)get_spin_virt_addr(); 301 volatile u32 bpcr; 302 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 303 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 304 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 305 u32 devdisr; 306 int timeout = 10; 307 308 whoami = in_be32(&pic->whoami); 309 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); 310 311 /* disable time base at the platform */ 312 devdisr = in_be32(&gur->devdisr); 313 if (whoami) 314 devdisr |= MPC85xx_DEVDISR_TB0; 315 else 316 devdisr |= MPC85xx_DEVDISR_TB1; 317 out_be32(&gur->devdisr, devdisr); 318 319 /* release the hounds */ 320 up = ((1 << cpu_numcores()) - 1); 321 bpcr = in_be32(&ecm->eebpcr); 322 bpcr |= (up << 24); 323 out_be32(&ecm->eebpcr, bpcr); 324 asm("sync; isync; msync"); 325 326 cpu_up_mask = 1 << whoami; 327 /* wait for everyone */ 328 while (timeout) { 329 int i; 330 for (i = 0; i < cpu_numcores(); i++) { 331 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 332 cpu_up_mask |= (1 << i); 333 }; 334 335 if ((cpu_up_mask & up) == up) 336 break; 337 338 udelay(100); 339 timeout--; 340 } 341 342 if (timeout == 0) 343 printf("CPU up timeout. CPU up mask is %x should be %x\n", 344 cpu_up_mask, up); 345 346 /* enable time base at the platform */ 347 if (whoami) 348 devdisr |= MPC85xx_DEVDISR_TB1; 349 else 350 devdisr |= MPC85xx_DEVDISR_TB0; 351 out_be32(&gur->devdisr, devdisr); 352 353 /* readback to sync write */ 354 in_be32(&gur->devdisr); 355 356 mtspr(SPRN_TBWU, 0); 357 mtspr(SPRN_TBWL, 0); 358 359 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); 360 out_be32(&gur->devdisr, devdisr); 361 362 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 363 /* 364 * Disabling Boot Page Translation allows the memory region 0xfffff000 365 * to 0xffffffff to be used normally. Leaving Boot Page Translation 366 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 367 * unusable for normal operation but it does allow OSes to easily 368 * reset a processor core to put it back into U-Boot's spinloop. 369 */ 370 clrbits_be32(&ecm->bptr, 0x80000000); 371 #endif 372 } 373 #endif 374 375 void cpu_mp_lmb_reserve(struct lmb *lmb) 376 { 377 u32 bootpg = determine_mp_bootpg(); 378 379 lmb_reserve(lmb, bootpg, 4096); 380 } 381 382 void setup_mp(void) 383 { 384 extern ulong __secondary_start_page; 385 extern ulong __bootpg_addr; 386 ulong fixup = (ulong)&__secondary_start_page; 387 u32 bootpg = determine_mp_bootpg(); 388 389 /* Some OSes expect secondary cores to be held in reset */ 390 if (hold_cores_in_reset(0)) 391 return; 392 393 /* Store the bootpg's SDRAM address for use by secondary CPU cores */ 394 __bootpg_addr = bootpg; 395 396 /* look for the tlb covering the reset page, there better be one */ 397 int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); 398 399 /* we found a match */ 400 if (i != -1) { 401 /* map reset page to bootpg so we can copy code there */ 402 disable_tlb(i); 403 404 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ 405 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 406 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ 407 408 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); 409 410 plat_mp_up(bootpg); 411 } else { 412 puts("WARNING: No reset page TLB. " 413 "Skipping secondary core setup\n"); 414 } 415 } 416