xref: /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/mp.c (revision 0cb77bfa)
1 /*
2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #include <common.h>
24 #include <asm/processor.h>
25 #include <ioports.h>
26 #include <lmb.h>
27 #include <asm/io.h>
28 #include <asm/mmu.h>
29 #include <asm/fsl_law.h>
30 #include "mp.h"
31 
32 DECLARE_GLOBAL_DATA_PTR;
33 
34 u32 get_my_id()
35 {
36 	return mfspr(SPRN_PIR);
37 }
38 
39 /*
40  * Determine if U-Boot should keep secondary cores in reset, or let them out
41  * of reset and hold them in a spinloop
42  */
43 int hold_cores_in_reset(int verbose)
44 {
45 	const char *s = getenv("mp_holdoff");
46 
47 	/* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
48 	if (s && (*s == 'y' || *s == 'Y' || *s == '1')) {
49 		if (verbose) {
50 			puts("Secondary cores are being held in reset.\n");
51 			puts("See 'mp_holdoff' environment variable\n");
52 		}
53 
54 		return 1;
55 	}
56 
57 	return 0;
58 }
59 
60 int cpu_reset(int nr)
61 {
62 	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
63 	out_be32(&pic->pir, 1 << nr);
64 	/* the dummy read works around an errata on early 85xx MP PICs */
65 	(void)in_be32(&pic->pir);
66 	out_be32(&pic->pir, 0x0);
67 
68 	return 0;
69 }
70 
71 int cpu_status(int nr)
72 {
73 	u32 *table, id = get_my_id();
74 
75 	if (hold_cores_in_reset(1))
76 		return 0;
77 
78 	if (nr == id) {
79 		table = (u32 *)get_spin_virt_addr();
80 		printf("table base @ 0x%p\n", table);
81 	} else {
82 		table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
83 		printf("Running on cpu %d\n", id);
84 		printf("\n");
85 		printf("table @ 0x%p\n", table);
86 		printf("   addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
87 		printf("   pir  - 0x%08x\n", table[BOOT_ENTRY_PIR]);
88 		printf("   r3   - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
89 		printf("   r6   - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
90 	}
91 
92 	return 0;
93 }
94 
95 #ifdef CONFIG_FSL_CORENET
96 int cpu_disable(int nr)
97 {
98 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
99 
100 	setbits_be32(&gur->coredisrl, 1 << nr);
101 
102 	return 0;
103 }
104 
105 int is_core_disabled(int nr) {
106 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
107 	u32 coredisrl = in_be32(&gur->coredisrl);
108 
109 	return (coredisrl & (1 << nr));
110 }
111 #else
112 int cpu_disable(int nr)
113 {
114 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
115 
116 	switch (nr) {
117 	case 0:
118 		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
119 		break;
120 	case 1:
121 		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
122 		break;
123 	default:
124 		printf("Invalid cpu number for disable %d\n", nr);
125 		return 1;
126 	}
127 
128 	return 0;
129 }
130 
131 int is_core_disabled(int nr) {
132 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
133 	u32 devdisr = in_be32(&gur->devdisr);
134 
135 	switch (nr) {
136 	case 0:
137 		return (devdisr & MPC85xx_DEVDISR_CPU0);
138 	case 1:
139 		return (devdisr & MPC85xx_DEVDISR_CPU1);
140 	default:
141 		printf("Invalid cpu number for disable %d\n", nr);
142 	}
143 
144 	return 0;
145 }
146 #endif
147 
148 static u8 boot_entry_map[4] = {
149 	0,
150 	BOOT_ENTRY_PIR,
151 	BOOT_ENTRY_R3_LOWER,
152 	BOOT_ENTRY_R6_LOWER,
153 };
154 
155 int cpu_release(int nr, int argc, char * const argv[])
156 {
157 	u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
158 	u64 boot_addr;
159 
160 	if (hold_cores_in_reset(1))
161 		return 0;
162 
163 	if (nr == get_my_id()) {
164 		printf("Invalid to release the boot core.\n\n");
165 		return 1;
166 	}
167 
168 	if (argc != 4) {
169 		printf("Invalid number of arguments to release.\n\n");
170 		return 1;
171 	}
172 
173 	boot_addr = simple_strtoull(argv[0], NULL, 16);
174 
175 	/* handle pir, r3, r6 */
176 	for (i = 1; i < 4; i++) {
177 		if (argv[i][0] != '-') {
178 			u8 entry = boot_entry_map[i];
179 			val = simple_strtoul(argv[i], NULL, 16);
180 			table[entry] = val;
181 		}
182 	}
183 
184 	table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
185 
186 	/* ensure all table updates complete before final address write */
187 	eieio();
188 
189 	table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
190 
191 	return 0;
192 }
193 
194 u32 determine_mp_bootpg(void)
195 {
196 	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
197 	if ((u64)gd->ram_size > 0xfffff000)
198 		return (0xfffff000);
199 
200 	return (gd->ram_size - 4096);
201 }
202 
203 ulong get_spin_phys_addr(void)
204 {
205 	extern ulong __secondary_start_page;
206 	extern ulong __spin_table;
207 
208 	return (determine_mp_bootpg() +
209 		(ulong)&__spin_table - (ulong)&__secondary_start_page);
210 }
211 
212 ulong get_spin_virt_addr(void)
213 {
214 	extern ulong __secondary_start_page;
215 	extern ulong __spin_table;
216 
217 	return (CONFIG_BPTR_VIRT_ADDR +
218 		(ulong)&__spin_table - (ulong)&__secondary_start_page);
219 }
220 
221 #ifdef CONFIG_FSL_CORENET
222 static void plat_mp_up(unsigned long bootpg)
223 {
224 	u32 up, cpu_up_mask, whoami;
225 	u32 *table = (u32 *)get_spin_virt_addr();
226 	volatile ccsr_gur_t *gur;
227 	volatile ccsr_local_t *ccm;
228 	volatile ccsr_rcpm_t *rcpm;
229 	volatile ccsr_pic_t *pic;
230 	int timeout = 10;
231 	u32 nr_cpus;
232 	struct law_entry e;
233 
234 	gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
235 	ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
236 	rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
237 	pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
238 
239 	nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
240 
241 	whoami = in_be32(&pic->whoami);
242 	cpu_up_mask = 1 << whoami;
243 	out_be32(&ccm->bstrl, bootpg);
244 
245 	e = find_law(bootpg);
246 	out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
247 
248 	/* readback to sync write */
249 	in_be32(&ccm->bstrar);
250 
251 	/* disable time base at the platform */
252 	out_be32(&rcpm->ctbenrl, cpu_up_mask);
253 
254 	/* release the hounds */
255 	up = ((1 << nr_cpus) - 1);
256 	out_be32(&gur->brrl, up);
257 
258 	/* wait for everyone */
259 	while (timeout) {
260 		int i;
261 		for (i = 0; i < nr_cpus; i++) {
262 			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
263 				cpu_up_mask |= (1 << i);
264 		};
265 
266 		if ((cpu_up_mask & up) == up)
267 			break;
268 
269 		udelay(100);
270 		timeout--;
271 	}
272 
273 	if (timeout == 0)
274 		printf("CPU up timeout. CPU up mask is %x should be %x\n",
275 			cpu_up_mask, up);
276 
277 	/* enable time base at the platform */
278 	out_be32(&rcpm->ctbenrl, 0);
279 
280 	/* readback to sync write */
281 	in_be32(&rcpm->ctbenrl);
282 
283 	mtspr(SPRN_TBWU, 0);
284 	mtspr(SPRN_TBWL, 0);
285 
286 	out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
287 
288 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
289 	/*
290 	 * Disabling Boot Page Translation allows the memory region 0xfffff000
291 	 * to 0xffffffff to be used normally.  Leaving Boot Page Translation
292 	 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
293 	 * unusable for normal operation but it does allow OSes to easily
294 	 * reset a processor core to put it back into U-Boot's spinloop.
295 	 */
296 	clrbits_be32(&ccm->bstrar, LAW_EN);
297 #endif
298 }
299 #else
300 static void plat_mp_up(unsigned long bootpg)
301 {
302 	u32 up, cpu_up_mask, whoami;
303 	u32 *table = (u32 *)get_spin_virt_addr();
304 	volatile u32 bpcr;
305 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
306 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
307 	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
308 	u32 devdisr;
309 	int timeout = 10;
310 
311 	whoami = in_be32(&pic->whoami);
312 	out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
313 
314 	/* disable time base at the platform */
315 	devdisr = in_be32(&gur->devdisr);
316 	if (whoami)
317 		devdisr |= MPC85xx_DEVDISR_TB0;
318 	else
319 		devdisr |= MPC85xx_DEVDISR_TB1;
320 	out_be32(&gur->devdisr, devdisr);
321 
322 	/* release the hounds */
323 	up = ((1 << cpu_numcores()) - 1);
324 	bpcr = in_be32(&ecm->eebpcr);
325 	bpcr |= (up << 24);
326 	out_be32(&ecm->eebpcr, bpcr);
327 	asm("sync; isync; msync");
328 
329 	cpu_up_mask = 1 << whoami;
330 	/* wait for everyone */
331 	while (timeout) {
332 		int i;
333 		for (i = 0; i < cpu_numcores(); i++) {
334 			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
335 				cpu_up_mask |= (1 << i);
336 		};
337 
338 		if ((cpu_up_mask & up) == up)
339 			break;
340 
341 		udelay(100);
342 		timeout--;
343 	}
344 
345 	if (timeout == 0)
346 		printf("CPU up timeout. CPU up mask is %x should be %x\n",
347 			cpu_up_mask, up);
348 
349 	/* enable time base at the platform */
350 	if (whoami)
351 		devdisr |= MPC85xx_DEVDISR_TB1;
352 	else
353 		devdisr |= MPC85xx_DEVDISR_TB0;
354 	out_be32(&gur->devdisr, devdisr);
355 
356 	/* readback to sync write */
357 	in_be32(&gur->devdisr);
358 
359 	mtspr(SPRN_TBWU, 0);
360 	mtspr(SPRN_TBWL, 0);
361 
362 	devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
363 	out_be32(&gur->devdisr, devdisr);
364 
365 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
366 	/*
367 	 * Disabling Boot Page Translation allows the memory region 0xfffff000
368 	 * to 0xffffffff to be used normally.  Leaving Boot Page Translation
369 	 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
370 	 * unusable for normal operation but it does allow OSes to easily
371 	 * reset a processor core to put it back into U-Boot's spinloop.
372 	 */
373 	clrbits_be32(&ecm->bptr, 0x80000000);
374 #endif
375 }
376 #endif
377 
378 void cpu_mp_lmb_reserve(struct lmb *lmb)
379 {
380 	u32 bootpg = determine_mp_bootpg();
381 
382 	lmb_reserve(lmb, bootpg, 4096);
383 }
384 
385 void setup_mp(void)
386 {
387 	extern ulong __secondary_start_page;
388 	extern ulong __bootpg_addr;
389 	ulong fixup = (ulong)&__secondary_start_page;
390 	u32 bootpg = determine_mp_bootpg();
391 
392 	/* Some OSes expect secondary cores to be held in reset */
393 	if (hold_cores_in_reset(0))
394 		return;
395 
396 	/* Store the bootpg's SDRAM address for use by secondary CPU cores */
397 	__bootpg_addr = bootpg;
398 
399 	/* look for the tlb covering the reset page, there better be one */
400 	int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
401 
402 	/* we found a match */
403 	if (i != -1) {
404 		/* map reset page to bootpg so we can copy code there */
405 		disable_tlb(i);
406 
407 		set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
408 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
409 			0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
410 
411 		memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
412 
413 		plat_mp_up(bootpg);
414 	} else {
415 		puts("WARNING: No reset page TLB. "
416 			"Skipping secondary core setup\n");
417 	}
418 }
419