1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/processor.h> 25 #include <ioports.h> 26 #include <lmb.h> 27 #include <asm/io.h> 28 #include <asm/mmu.h> 29 #include <asm/fsl_law.h> 30 #include <asm/fsl_ddr_sdram.h> 31 #include "mp.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 u32 fsl_ddr_get_intl3r(void); 35 36 extern u32 __spin_table[]; 37 38 u32 get_my_id() 39 { 40 return mfspr(SPRN_PIR); 41 } 42 43 /* 44 * Determine if U-Boot should keep secondary cores in reset, or let them out 45 * of reset and hold them in a spinloop 46 */ 47 int hold_cores_in_reset(int verbose) 48 { 49 /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */ 50 if (getenv_yesno("mp_holdoff") == 1) { 51 if (verbose) { 52 puts("Secondary cores are being held in reset.\n"); 53 puts("See 'mp_holdoff' environment variable\n"); 54 } 55 56 return 1; 57 } 58 59 return 0; 60 } 61 62 int cpu_reset(int nr) 63 { 64 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 65 out_be32(&pic->pir, 1 << nr); 66 /* the dummy read works around an errata on early 85xx MP PICs */ 67 (void)in_be32(&pic->pir); 68 out_be32(&pic->pir, 0x0); 69 70 return 0; 71 } 72 73 int cpu_status(int nr) 74 { 75 u32 *table, id = get_my_id(); 76 77 if (hold_cores_in_reset(1)) 78 return 0; 79 80 if (nr == id) { 81 table = (u32 *)&__spin_table; 82 printf("table base @ 0x%p\n", table); 83 } else if (is_core_disabled(nr)) { 84 puts("Disabled\n"); 85 } else { 86 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; 87 printf("Running on cpu %d\n", id); 88 printf("\n"); 89 printf("table @ 0x%p\n", table); 90 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); 91 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); 92 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); 93 } 94 95 return 0; 96 } 97 98 #ifdef CONFIG_FSL_CORENET 99 int cpu_disable(int nr) 100 { 101 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 102 103 setbits_be32(&gur->coredisrl, 1 << nr); 104 105 return 0; 106 } 107 108 int is_core_disabled(int nr) { 109 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 110 u32 coredisrl = in_be32(&gur->coredisrl); 111 112 return (coredisrl & (1 << nr)); 113 } 114 #else 115 int cpu_disable(int nr) 116 { 117 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 118 119 switch (nr) { 120 case 0: 121 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); 122 break; 123 case 1: 124 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); 125 break; 126 default: 127 printf("Invalid cpu number for disable %d\n", nr); 128 return 1; 129 } 130 131 return 0; 132 } 133 134 int is_core_disabled(int nr) { 135 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 136 u32 devdisr = in_be32(&gur->devdisr); 137 138 switch (nr) { 139 case 0: 140 return (devdisr & MPC85xx_DEVDISR_CPU0); 141 case 1: 142 return (devdisr & MPC85xx_DEVDISR_CPU1); 143 default: 144 printf("Invalid cpu number for disable %d\n", nr); 145 } 146 147 return 0; 148 } 149 #endif 150 151 static u8 boot_entry_map[4] = { 152 0, 153 BOOT_ENTRY_PIR, 154 BOOT_ENTRY_R3_LOWER, 155 }; 156 157 int cpu_release(int nr, int argc, char * const argv[]) 158 { 159 u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; 160 u64 boot_addr; 161 162 if (hold_cores_in_reset(1)) 163 return 0; 164 165 if (nr == get_my_id()) { 166 printf("Invalid to release the boot core.\n\n"); 167 return 1; 168 } 169 170 if (argc != 4) { 171 printf("Invalid number of arguments to release.\n\n"); 172 return 1; 173 } 174 175 boot_addr = simple_strtoull(argv[0], NULL, 16); 176 177 /* handle pir, r3 */ 178 for (i = 1; i < 3; i++) { 179 if (argv[i][0] != '-') { 180 u8 entry = boot_entry_map[i]; 181 val = simple_strtoul(argv[i], NULL, 16); 182 table[entry] = val; 183 } 184 } 185 186 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); 187 188 /* ensure all table updates complete before final address write */ 189 eieio(); 190 191 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); 192 193 return 0; 194 } 195 196 u32 determine_mp_bootpg(unsigned int *pagesize) 197 { 198 u32 bootpg; 199 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 200 u32 svr = get_svr(); 201 u32 granule_size, check; 202 struct law_entry e; 203 #endif 204 205 206 /* use last 4K of mapped memory */ 207 bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? 208 CONFIG_MAX_MEM_MAPPED : gd->ram_size) + 209 CONFIG_SYS_SDRAM_BASE - 4096; 210 if (pagesize) 211 *pagesize = 4096; 212 213 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 214 /* 215 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240, 216 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But 217 * the way boot page chosen in u-boot avoids hitting this erratum. So only 218 * thw workaround for 3-way interleaving is needed. 219 * 220 * To make sure boot page translation works with 3-Way DDR interleaving 221 * enforce a check for the following constrains 222 * 8K granule size requires BRSIZE=8K and 223 * bootpg >> log2(BRSIZE) %3 == 1 224 * 4K and 1K granule size requires BRSIZE=4K and 225 * bootpg >> log2(BRSIZE) %3 == 0 226 */ 227 if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) { 228 e = find_law(bootpg); 229 switch (e.trgt_id) { 230 case LAW_TRGT_IF_DDR_INTLV_123: 231 granule_size = fsl_ddr_get_intl3r() & 0x1f; 232 if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) { 233 if (pagesize) 234 *pagesize = 8192; 235 bootpg &= 0xffffe000; /* align to 8KB */ 236 check = bootpg >> 13; 237 while ((check % 3) != 1) 238 check--; 239 bootpg = check << 13; 240 debug("Boot page (8K) at 0x%08x\n", bootpg); 241 break; 242 } else { 243 bootpg &= 0xfffff000; /* align to 4KB */ 244 check = bootpg >> 12; 245 while ((check % 3) != 0) 246 check--; 247 bootpg = check << 12; 248 debug("Boot page (4K) at 0x%08x\n", bootpg); 249 } 250 break; 251 default: 252 break; 253 } 254 } 255 #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */ 256 257 return bootpg; 258 } 259 260 phys_addr_t get_spin_phys_addr(void) 261 { 262 return virt_to_phys(&__spin_table); 263 } 264 265 #ifdef CONFIG_FSL_CORENET 266 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) 267 { 268 u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K; 269 u32 *table = (u32 *)&__spin_table; 270 volatile ccsr_gur_t *gur; 271 volatile ccsr_local_t *ccm; 272 volatile ccsr_rcpm_t *rcpm; 273 volatile ccsr_pic_t *pic; 274 int timeout = 10; 275 u32 mask = cpu_mask(); 276 struct law_entry e; 277 278 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 279 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); 280 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 281 pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 282 283 whoami = in_be32(&pic->whoami); 284 cpu_up_mask = 1 << whoami; 285 out_be32(&ccm->bstrl, bootpg); 286 287 e = find_law(bootpg); 288 /* pagesize is only 4K or 8K */ 289 if (pagesize == 8192) 290 brsize = LAW_SIZE_8K; 291 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize); 292 debug("BRSIZE is 0x%x\n", brsize); 293 294 /* readback to sync write */ 295 in_be32(&ccm->bstrar); 296 297 /* disable time base at the platform */ 298 out_be32(&rcpm->ctbenrl, cpu_up_mask); 299 300 out_be32(&gur->brrl, mask); 301 302 /* wait for everyone */ 303 while (timeout) { 304 unsigned int i, cpu, nr_cpus = cpu_numcores(); 305 306 for_each_cpu(i, cpu, nr_cpus, mask) { 307 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 308 cpu_up_mask |= (1 << cpu); 309 } 310 311 if ((cpu_up_mask & mask) == mask) 312 break; 313 314 udelay(100); 315 timeout--; 316 } 317 318 if (timeout == 0) 319 printf("CPU up timeout. CPU up mask is %x should be %x\n", 320 cpu_up_mask, mask); 321 322 /* enable time base at the platform */ 323 out_be32(&rcpm->ctbenrl, 0); 324 325 /* readback to sync write */ 326 in_be32(&rcpm->ctbenrl); 327 328 mtspr(SPRN_TBWU, 0); 329 mtspr(SPRN_TBWL, 0); 330 331 out_be32(&rcpm->ctbenrl, mask); 332 333 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 334 /* 335 * Disabling Boot Page Translation allows the memory region 0xfffff000 336 * to 0xffffffff to be used normally. Leaving Boot Page Translation 337 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 338 * unusable for normal operation but it does allow OSes to easily 339 * reset a processor core to put it back into U-Boot's spinloop. 340 */ 341 clrbits_be32(&ccm->bstrar, LAW_EN); 342 #endif 343 } 344 #else 345 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) 346 { 347 u32 up, cpu_up_mask, whoami; 348 u32 *table = (u32 *)&__spin_table; 349 volatile u32 bpcr; 350 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 351 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 352 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 353 u32 devdisr; 354 int timeout = 10; 355 356 whoami = in_be32(&pic->whoami); 357 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); 358 359 /* disable time base at the platform */ 360 devdisr = in_be32(&gur->devdisr); 361 if (whoami) 362 devdisr |= MPC85xx_DEVDISR_TB0; 363 else 364 devdisr |= MPC85xx_DEVDISR_TB1; 365 out_be32(&gur->devdisr, devdisr); 366 367 /* release the hounds */ 368 up = ((1 << cpu_numcores()) - 1); 369 bpcr = in_be32(&ecm->eebpcr); 370 bpcr |= (up << 24); 371 out_be32(&ecm->eebpcr, bpcr); 372 asm("sync; isync; msync"); 373 374 cpu_up_mask = 1 << whoami; 375 /* wait for everyone */ 376 while (timeout) { 377 int i; 378 for (i = 0; i < cpu_numcores(); i++) { 379 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) 380 cpu_up_mask |= (1 << i); 381 }; 382 383 if ((cpu_up_mask & up) == up) 384 break; 385 386 udelay(100); 387 timeout--; 388 } 389 390 if (timeout == 0) 391 printf("CPU up timeout. CPU up mask is %x should be %x\n", 392 cpu_up_mask, up); 393 394 /* enable time base at the platform */ 395 if (whoami) 396 devdisr |= MPC85xx_DEVDISR_TB1; 397 else 398 devdisr |= MPC85xx_DEVDISR_TB0; 399 out_be32(&gur->devdisr, devdisr); 400 401 /* readback to sync write */ 402 in_be32(&gur->devdisr); 403 404 mtspr(SPRN_TBWU, 0); 405 mtspr(SPRN_TBWL, 0); 406 407 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); 408 out_be32(&gur->devdisr, devdisr); 409 410 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR 411 /* 412 * Disabling Boot Page Translation allows the memory region 0xfffff000 413 * to 0xffffffff to be used normally. Leaving Boot Page Translation 414 * enabled remaps 0xfffff000 to SDRAM which makes that memory region 415 * unusable for normal operation but it does allow OSes to easily 416 * reset a processor core to put it back into U-Boot's spinloop. 417 */ 418 clrbits_be32(&ecm->bptr, 0x80000000); 419 #endif 420 } 421 #endif 422 423 void cpu_mp_lmb_reserve(struct lmb *lmb) 424 { 425 u32 bootpg = determine_mp_bootpg(NULL); 426 427 lmb_reserve(lmb, bootpg, 4096); 428 } 429 430 void setup_mp(void) 431 { 432 extern u32 __secondary_start_page; 433 extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page; 434 435 int i; 436 ulong fixup = (u32)&__secondary_start_page; 437 u32 bootpg, bootpg_map, pagesize; 438 439 bootpg = determine_mp_bootpg(&pagesize); 440 441 /* 442 * pagesize is only 4K or 8K 443 * we only use the last 4K of boot page 444 * bootpg_map saves the address for the boot page 445 * 8K is used for the workaround of 3-way DDR interleaving 446 */ 447 448 bootpg_map = bootpg; 449 450 if (pagesize == 8192) 451 bootpg += 4096; /* use 2nd half */ 452 453 /* Some OSes expect secondary cores to be held in reset */ 454 if (hold_cores_in_reset(0)) 455 return; 456 457 /* 458 * Store the bootpg's cache-able half address for use by secondary 459 * CPU cores to continue to boot 460 */ 461 __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page); 462 463 /* Store spin table's physical address for use by secondary cores */ 464 __spin_table_addr = (u32)get_spin_phys_addr(); 465 466 /* flush bootpg it before copying invalidate any staled cacheline */ 467 flush_cache(bootpg, 4096); 468 469 /* look for the tlb covering the reset page, there better be one */ 470 i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); 471 472 /* we found a match */ 473 if (i != -1) { 474 /* map reset page to bootpg so we can copy code there */ 475 disable_tlb(i); 476 477 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ 478 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 479 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ 480 481 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); 482 483 plat_mp_up(bootpg_map, pagesize); 484 } else { 485 puts("WARNING: No reset page TLB. " 486 "Skipping secondary core setup\n"); 487 } 488 } 489