1 /*
2  * (C) Copyright 2000-2002
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * (C) Copyright 2002 (440 port)
6  * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
7  *
8  * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
9  * Xianghua Xiao (X.Xiao@motorola.com)
10  *
11  * SPDX-License-Identifier:	GPL-2.0+
12  */
13 
14 #include <common.h>
15 #include <watchdog.h>
16 #include <command.h>
17 #include <asm/processor.h>
18 #include <asm/io.h>
19 #ifdef CONFIG_POST
20 #include <post.h>
21 #endif
22 
23 int interrupt_init_cpu(unsigned int *decrementer_count)
24 {
25 	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
26 
27 #ifdef CONFIG_POST
28 	/*
29 	 * The POST word is stored in the PIC's TFRR register which gets
30 	 * cleared when the PIC is reset.  Save it off so we can restore it
31 	 * later.
32 	 */
33 	ulong post_word = post_word_load();
34 #endif
35 
36 	out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
37 	while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
38 		;
39 	out_be32(&pic->gcr, MPC85xx_PICGCR_M);
40 	in_be32(&pic->gcr);
41 
42 	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
43 
44 	/* PIE is same as DIE, dec interrupt enable */
45 	mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
46 
47 #ifdef CONFIG_INTERRUPTS
48 	pic->iivpr1 = 0x810001;	/* 50220 enable ecm interrupts */
49 	debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
50 
51 	pic->iivpr2 = 0x810002;	/* 50240 enable ddr interrupts */
52 	debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
53 
54 	pic->iivpr3 = 0x810003;	/* 50260 enable lbc interrupts */
55 	debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
56 
57 #ifdef CONFIG_PCI1
58 	pic->iivpr8 = 0x810008;	/* enable pci1 interrupts */
59 	debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
60 #endif
61 #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
62 	pic->iivpr9 = 0x810009;	/* enable pci1 interrupts */
63 	debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
64 #endif
65 #ifdef CONFIG_PCIE1
66 	pic->iivpr10 = 0x81000a;	/* enable pcie1 interrupts */
67 	debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
68 #endif
69 #ifdef CONFIG_PCIE3
70 	pic->iivpr11 = 0x81000b;	/* enable pcie3 interrupts */
71 	debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
72 #endif
73 
74 	pic->ctpr=0;		/* 40080 clear current task priority register */
75 #endif
76 
77 #ifdef CONFIG_POST
78 	post_word_store(post_word);
79 #endif
80 
81 	return (0);
82 }
83 
84 /* Install and free a interrupt handler. Not implemented yet. */
85 
86 void
87 irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
88 {
89 	return;
90 }
91 
92 void
93 irq_free_handler(int vec)
94 {
95 	return;
96 }
97 
98 void timer_interrupt_cpu(struct pt_regs *regs)
99 {
100 	/* PIS is same as DIS, dec interrupt status */
101 	mtspr(SPRN_TSR, TSR_PIS);
102 }
103 
104 #if defined(CONFIG_CMD_IRQ)
105 /* irqinfo - print information about PCI devices,not implemented. */
106 int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
107 {
108 	return 0;
109 }
110 #endif
111