1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 25 #include <hwconfig.h> 26 #endif 27 #include <asm/fsl_serdes.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/io.h> 30 #include <asm/processor.h> 31 #include <asm/fsl_law.h> 32 #include <asm/errno.h> 33 #include "fsl_corenet_serdes.h" 34 35 /* 36 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together. 37 * The code is already very complicated as it is, and separating the two 38 * completely would just make things worse. We try to keep them as separate 39 * as possible, but for now we require SERDES8 if SERDES_A001 is defined. 40 */ 41 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 42 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8 43 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8" 44 #endif 45 #endif 46 47 static u32 serdes_prtcl_map; 48 49 #ifdef DEBUG 50 static const char *serdes_prtcl_str[] = { 51 [NONE] = "NA", 52 [PCIE1] = "PCIE1", 53 [PCIE2] = "PCIE2", 54 [PCIE3] = "PCIE3", 55 [PCIE4] = "PCIE4", 56 [SATA1] = "SATA1", 57 [SATA2] = "SATA2", 58 [SRIO1] = "SRIO1", 59 [SRIO2] = "SRIO2", 60 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", 61 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", 62 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", 63 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", 64 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", 65 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", 66 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", 67 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", 68 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", 69 [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5", 70 [XAUI_FM1] = "XAUI_FM1", 71 [XAUI_FM2] = "XAUI_FM2", 72 [AURORA] = "DEBUG", 73 }; 74 #endif 75 76 static const struct { 77 int idx; 78 unsigned int lpd; /* RCW lane powerdown bit */ 79 int bank; 80 } lanes[SRDS_MAX_LANES] = { 81 { 0, 152, FSL_SRDS_BANK_1 }, 82 { 1, 153, FSL_SRDS_BANK_1 }, 83 { 2, 154, FSL_SRDS_BANK_1 }, 84 { 3, 155, FSL_SRDS_BANK_1 }, 85 { 4, 156, FSL_SRDS_BANK_1 }, 86 { 5, 157, FSL_SRDS_BANK_1 }, 87 { 6, 158, FSL_SRDS_BANK_1 }, 88 { 7, 159, FSL_SRDS_BANK_1 }, 89 { 8, 160, FSL_SRDS_BANK_1 }, 90 { 9, 161, FSL_SRDS_BANK_1 }, 91 { 16, 162, FSL_SRDS_BANK_2 }, 92 { 17, 163, FSL_SRDS_BANK_2 }, 93 { 18, 164, FSL_SRDS_BANK_2 }, 94 { 19, 165, FSL_SRDS_BANK_2 }, 95 #ifdef CONFIG_PPC_P4080 96 { 20, 170, FSL_SRDS_BANK_3 }, 97 { 21, 171, FSL_SRDS_BANK_3 }, 98 { 22, 172, FSL_SRDS_BANK_3 }, 99 { 23, 173, FSL_SRDS_BANK_3 }, 100 #else 101 { 20, 166, FSL_SRDS_BANK_3 }, 102 { 21, 167, FSL_SRDS_BANK_3 }, 103 { 22, 168, FSL_SRDS_BANK_3 }, 104 { 23, 169, FSL_SRDS_BANK_3 }, 105 #endif 106 #if SRDS_MAX_BANK > 3 107 { 24, 175, FSL_SRDS_BANK_4 }, 108 { 25, 176, FSL_SRDS_BANK_4 }, 109 #endif 110 }; 111 112 int serdes_get_lane_idx(int lane) 113 { 114 return lanes[lane].idx; 115 } 116 117 int serdes_get_bank_by_lane(int lane) 118 { 119 return lanes[lane].bank; 120 } 121 122 int serdes_lane_enabled(int lane) 123 { 124 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 125 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 126 127 int bank = lanes[lane].bank; 128 int word = lanes[lane].lpd / 32; 129 int bit = lanes[lane].lpd % 32; 130 131 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) 132 return 0; 133 134 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 135 /* 136 * For banks two and three, use the srds_lpd_b[] array instead of the 137 * RCW, because this array contains the real values of SRDS_LPD_B2 and 138 * SRDS_LPD_B3. 139 */ 140 if (bank > 0) 141 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); 142 #endif 143 144 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); 145 } 146 147 int is_serdes_configured(enum srds_prtcl device) 148 { 149 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 150 151 /* Is serdes enabled at all? */ 152 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 153 return 0; 154 155 return (1 << device) & serdes_prtcl_map; 156 } 157 158 static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device) 159 { 160 int i; 161 162 for (i = 0; i < SRDS_MAX_LANES; i++) { 163 if (serdes_get_prtcl(prtcl, i) == device) 164 return i; 165 } 166 167 return -ENODEV; 168 } 169 170 /* 171 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given 172 * device. This depends on the current SERDES protocol, as defined in the RCW. 173 * 174 * Returns a negative error code if SERDES is disabled or the given device is 175 * not supported in the current SERDES protocol. 176 */ 177 int serdes_get_first_lane(enum srds_prtcl device) 178 { 179 u32 prtcl; 180 const ccsr_gur_t *gur; 181 182 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; 183 184 /* Is serdes enabled at all? */ 185 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) 186 return -ENODEV; 187 188 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 189 190 return __serdes_get_first_lane(prtcl, device); 191 } 192 193 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 194 /* 195 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given 196 * SERDES protocol. 197 * 198 * Returns a negative error code if the given device is not supported for the 199 * given SERDES protocol. 200 */ 201 static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device) 202 { 203 int lane; 204 205 lane = __serdes_get_first_lane(prtcl, device); 206 if (unlikely(lane < 0)) 207 return lane; 208 209 return serdes_get_bank_by_lane(lane); 210 } 211 212 static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device, 213 int first) 214 { 215 int lane; 216 217 for (lane = first; lane < SRDS_MAX_LANES; lane++) { 218 if (serdes_get_prtcl(prtcl, lane) != device) 219 break; 220 } 221 222 return lane - first; 223 } 224 225 static void __serdes_reset_rx(serdes_corenet_t *regs, 226 uint32_t prtcl, 227 enum srds_prtcl device) 228 { 229 int lane, idx, first, last; 230 231 lane = __serdes_get_first_lane(prtcl, device); 232 if (unlikely(lane < 0)) 233 return; 234 first = serdes_get_lane_idx(lane); 235 last = first + __serdes_get_lane_count(prtcl, device, lane); 236 237 /* 238 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is 239 * selected as XAUI to place the lane into reset. 240 */ 241 for (idx = first; idx < last; idx++) 242 clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); 243 244 /* Wait at least 250 ns */ 245 udelay(1); 246 247 /* 248 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is 249 * selected as XAUI to bring the lane out of reset. 250 */ 251 for (idx = first; idx < last; idx++) 252 setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); 253 } 254 255 void serdes_reset_rx(enum srds_prtcl device) 256 { 257 u32 prtcl; 258 const ccsr_gur_t *gur; 259 serdes_corenet_t *regs; 260 261 if (unlikely(device == NONE)) 262 return; 263 264 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; 265 266 /* Is serdes enabled at all? */ 267 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) 268 return; 269 270 regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 271 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 272 273 __serdes_reset_rx(regs, prtcl, device); 274 } 275 #endif 276 277 #ifndef CONFIG_SYS_DCSRBAR_PHYS 278 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ 279 #define CONFIG_SYS_DCSRBAR 0x80000000 280 #define __DCSR_NOT_DEFINED_BY_CONFIG 281 #endif 282 283 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 284 /* 285 * Enable a SERDES bank that was disabled via the RCW 286 * 287 * We only call this function for SERDES8 and SERDES-A001 in cases we really 288 * want to enable the bank, whether we actually want to use the lanes or not, 289 * so make sure at least one lane is enabled. We're only enabling this one 290 * lane to satisfy errata requirements that the bank be enabled. 291 * 292 * We use a local variable instead of srds_lpd_b[] because we want drivers to 293 * think that the lanes actually are disabled. 294 */ 295 static void enable_bank(ccsr_gur_t *gur, int bank) 296 { 297 u32 rcw5; 298 u32 temp_lpd_b = srds_lpd_b[bank]; 299 300 /* 301 * If we're asked to disable all lanes, just pretend we're doing 302 * that. 303 */ 304 if (temp_lpd_b == 0xF) 305 temp_lpd_b = 0xE; 306 307 /* 308 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in 309 * CCSR, and read/write in DSCR. 310 */ 311 rcw5 = in_be32(gur->rcwsr + 5); 312 if (bank == FSL_SRDS_BANK_2) { 313 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2; 314 rcw5 |= temp_lpd_b << 26; 315 } else if (bank == FSL_SRDS_BANK_3) { 316 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3; 317 rcw5 |= temp_lpd_b << 18; 318 } else { 319 printf("SERDES: enable_bank: bad bank %d\n", bank + 1); 320 return; 321 } 322 323 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation 324 * of the DCSR mapping. 325 */ 326 { 327 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 328 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); 329 int law_index; 330 if (law.index == -1) 331 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, 332 LAW_SIZE_1M, LAW_TRGT_IF_DCSR); 333 else 334 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, 335 LAW_TRGT_IF_DCSR); 336 #endif 337 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; 338 out_be32(p, rcw5); 339 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 340 if (law.index == -1) 341 disable_law(law_index); 342 else 343 set_law(law.index, law.addr, law.size, law.trgt_id); 344 #endif 345 } 346 } 347 348 /* 349 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from 350 * bank 3 to clock banks 2 and 3, as well as a limited selection of 351 * protocol configurations. This requires that banks 2 and 3's lanes be 352 * disabled in the RCW, and enabled with some fixup here to re-enable 353 * them, and to configure bank 2's clock parameters in bank 3's pll in 354 * cases where they differ. 355 */ 356 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, 357 u32 devdisr, u32 devdisr2, int cfg) 358 { 359 int srds_ratio_b2; 360 int rfck_sel; 361 362 /* 363 * The disabled lanes of bank 2 will cause the associated 364 * logic blocks to be disabled in DEVDISR. We reverse that here. 365 * 366 * Note that normally it is not permitted to clear DEVDISR bits 367 * once the device has been disabled, but the hardware people 368 * say that this special case is OK. 369 */ 370 clrbits_be32(&gur->devdisr, devdisr); 371 clrbits_be32(&gur->devdisr2, devdisr2); 372 373 /* 374 * Some protocols require special handling. There are a few 375 * additional protocol configurations that can be used, which are 376 * not listed here. See app note 4065 for supported protocol 377 * configurations. 378 */ 379 switch (cfg) { 380 case 0x19: 381 /* 382 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL. 383 * SGMII on bank 3 should still be usable. 384 */ 385 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, 386 SRDS_PLLCR1_PLL_BWSEL); 387 break; 388 389 case 0x0f: 390 case 0x10: 391 /* 392 * Banks 2 (XAUI) and 3 (SGMII) have different clocking 393 * requirements in these configurations. Bank 3 cannot 394 * be used and should have its lanes (but not the bank 395 * itself) disabled in the RCW. We set up bank 3's pll 396 * for bank 2's needs here. 397 */ 398 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7; 399 400 /* Determine refclock from XAUI ratio */ 401 switch (srds_ratio_b2) { 402 case 1: /* 20:1 */ 403 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25; 404 break; 405 case 2: /* 25:1 */ 406 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125; 407 break; 408 default: 409 printf("SERDES: bad SRDS_RATIO_B2 %d\n", 410 srds_ratio_b2); 411 return; 412 } 413 414 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 415 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel); 416 417 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 418 SRDS_PLLCR0_FRATE_SEL_MASK, 419 SRDS_PLLCR0_FRATE_SEL_6_25); 420 break; 421 } 422 423 enable_bank(gur, FSL_SRDS_BANK_3); 424 } 425 #endif 426 427 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 428 /* 429 * If PCIe is not selected as a protocol for any lanes driven by a given PLL, 430 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0. 431 */ 432 static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) 433 { 434 enum srds_prtcl device; 435 436 switch (cfg) { 437 case 0x13: 438 case 0x16: 439 /* 440 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL] 441 * to 0. 442 */ 443 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, 444 SRDS_PLLCR1_PLL_BWSEL); 445 break; 446 case 0x19: 447 /* 448 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and 449 * SRDSB3PLLCR1[PLLBW_SEL] to 1. 450 */ 451 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, 452 SRDS_PLLCR1_PLL_BWSEL); 453 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, 454 SRDS_PLLCR1_PLL_BWSEL); 455 break; 456 } 457 458 /* 459 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI 460 * before XAUI is initialized. 461 */ 462 for (device = XAUI_FM1; device <= XAUI_FM2; device++) { 463 if (is_serdes_configured(device)) { 464 int bank = serdes_get_bank_by_device(cfg, device); 465 466 clrbits_be32(®s->bank[bank].pllcr1, 467 SRDS_PLLCR1_PLL_BWSEL); 468 } 469 } 470 } 471 #endif 472 473 /* 474 * Wait for the RSTDONE bit to get set, or a one-second timeout. 475 */ 476 static void wait_for_rstdone(unsigned int bank) 477 { 478 serdes_corenet_t *srds_regs = 479 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 480 unsigned long long end_tick; 481 u32 rstctl; 482 483 /* wait for reset complete or 1-second timeout */ 484 end_tick = usec2ticks(1000000) + get_ticks(); 485 do { 486 rstctl = in_be32(&srds_regs->bank[bank].rstctl); 487 if (rstctl & SRDS_RSTCTL_RSTDONE) 488 break; 489 } while (end_tick > get_ticks()); 490 491 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) 492 printf("SERDES: timeout resetting bank %u\n", bank + 1); 493 } 494 495 496 static void __soc_serdes_init(void) 497 { 498 /* Allow for SoC-specific initialization in <SOC>_serdes.c */ 499 }; 500 void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init"))); 501 502 void fsl_serdes_init(void) 503 { 504 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 505 int cfg; 506 serdes_corenet_t *srds_regs; 507 #ifdef CONFIG_PPC_P5040 508 serdes_corenet_t *srds2_regs; 509 #endif 510 int lane, bank, idx; 511 int have_bank[SRDS_MAX_BANK] = {}; 512 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 513 u32 serdes8_devdisr = 0; 514 u32 serdes8_devdisr2 = 0; 515 char srds_lpd_opt[16]; 516 const char *srds_lpd_arg; 517 size_t arglen; 518 #endif 519 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 520 int need_serdes_a001; /* true == need work-around for SERDES A001 */ 521 #endif 522 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 523 char buffer[HWCONFIG_BUFFER_SIZE]; 524 char *buf = NULL; 525 526 /* 527 * Extract hwconfig from environment since we have not properly setup 528 * the environment but need it for ddr config params 529 */ 530 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) 531 buf = buffer; 532 #endif 533 534 /* Is serdes enabled at all? */ 535 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 536 return; 537 538 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); 539 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 540 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg); 541 542 if (!is_serdes_prtcl_valid(cfg)) { 543 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg); 544 return; 545 } 546 547 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 548 /* 549 * Display a warning if banks two and three are not disabled in the RCW, 550 * since our work-around for SERDES8 depends on these banks being 551 * disabled at power-on. 552 */ 553 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3) 554 if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) { 555 printf("Warning: SERDES8 requires banks two and " 556 "three to be disabled in the RCW\n"); 557 } 558 559 /* 560 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3 561 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds 562 * for a description of these options. 563 */ 564 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { 565 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); 566 srds_lpd_arg = 567 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf); 568 if (srds_lpd_arg) 569 srds_lpd_b[bank] = 570 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf; 571 } 572 573 if ((cfg == 0xf) || (cfg == 0x10)) { 574 /* 575 * For SERDES protocols 0xF and 0x10, force bank 3 to be 576 * disabled, because it is not supported. 577 */ 578 srds_lpd_b[FSL_SRDS_BANK_3] = 0xF; 579 } 580 #endif 581 582 /* Look for banks with all lanes disabled, and power down the bank. */ 583 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 584 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); 585 if (serdes_lane_enabled(lane)) { 586 have_bank[serdes_get_bank_by_lane(lane)] = 1; 587 serdes_prtcl_map |= (1 << lane_prtcl); 588 } 589 } 590 591 #ifdef CONFIG_PPC_P5040 592 /* 593 * Lanes on bank 4 on P5040 are commented-out, but for some SERDES 594 * protocols, these lanes are routed to SATA. We use serdes_prtcl_map 595 * to decide whether a protocol is supported on a given lane, so SATA 596 * will be identified as not supported, and therefore not initialized. 597 * So for protocols which use SATA on bank4, we add SATA support in 598 * serdes_prtcl_map. 599 */ 600 switch (cfg) { 601 case 0x0: 602 case 0x1: 603 case 0x2: 604 case 0x3: 605 case 0x4: 606 case 0x5: 607 case 0x6: 608 case 0x7: 609 serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2; 610 break; 611 default: 612 srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; 613 614 /* We don't need bank 4, so power it down */ 615 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); 616 } 617 #endif 618 619 soc_serdes_init(); 620 621 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 622 /* 623 * Bank two uses the clock from bank three, so if bank two is enabled, 624 * then bank three must also be enabled. 625 */ 626 if (have_bank[FSL_SRDS_BANK_2]) 627 have_bank[FSL_SRDS_BANK_3] = 1; 628 #endif 629 630 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 631 /* 632 * The work-aroud for erratum SERDES-A001 is needed only if bank two 633 * is disabled and bank three is enabled. The converse is also true, 634 * but SERDES8 ensures that bank 3 is always enabled if bank 2 is 635 * enabled, so there's no point in complicating the code to handle 636 * that situation. 637 */ 638 need_serdes_a001 = 639 !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; 640 #endif 641 642 /* Power down the banks we're not interested in */ 643 for (bank = 0; bank < SRDS_MAX_BANK; bank++) { 644 if (!have_bank[bank]) { 645 printf("SERDES: bank %d disabled\n", bank + 1); 646 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 647 /* 648 * Erratum SERDES-A001 says bank two needs to be powered 649 * down after bank three is powered up, so don't power 650 * down bank two here. 651 */ 652 if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2)) 653 setbits_be32(&srds_regs->bank[bank].rstctl, 654 SRDS_RSTCTL_SDPD); 655 #else 656 setbits_be32(&srds_regs->bank[bank].rstctl, 657 SRDS_RSTCTL_SDPD); 658 #endif 659 } 660 } 661 662 #ifdef CONFIG_SYS_FSL_ERRATUM_A004699 663 /* 664 * To avoid the situation that resulted in the P4080 erratum 665 * SERDES-8, a given SerDes bank will use the PLLs from the previous 666 * bank if one of the PLL frequencies is a multiple of the other. For 667 * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz, 668 * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says 669 * that, in this situation, lane synchronization is not initiated. So 670 * when we detect a bank with a "borrowed" PLL, we have to manually 671 * initiate lane synchronization. 672 */ 673 for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) { 674 /* Determine the first lane for this bank */ 675 unsigned int lane; 676 677 for (lane = 0; lane < SRDS_MAX_LANES; lane++) 678 if (lanes[lane].bank == bank) 679 break; 680 idx = lanes[lane].idx; 681 682 /* 683 * Check if the PLL for the bank is borrowed. The UOTHL 684 * bit of the first lane will tell us that. 685 */ 686 if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) { 687 /* Manually start lane synchronization */ 688 setbits_be32(&srds_regs->bank[bank].pllcr0, 689 SRDS_PLLCR0_PVCOCNT_EN); 690 } 691 } 692 #endif 693 694 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) 695 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 696 enum srds_prtcl lane_prtcl; 697 698 idx = serdes_get_lane_idx(lane); 699 lane_prtcl = serdes_get_prtcl(cfg, lane); 700 701 #ifdef DEBUG 702 switch (lane) { 703 case 0: 704 puts("Bank1: "); 705 break; 706 case 10: 707 puts("\nBank2: "); 708 break; 709 case 14: 710 puts("\nBank3: "); 711 break; 712 default: 713 break; 714 } 715 716 printf("%s ", serdes_prtcl_str[lane_prtcl]); 717 #endif 718 719 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 720 /* 721 * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1 722 * for each of the SerDes lanes selected as SGMII, XAUI, SRIO, 723 * or AURORA before the device is initialized. 724 * 725 * Note that this part of the SERDES-9 work-around is 726 * redundant if the work-around for A-4580 has already been 727 * applied via PBI. 728 */ 729 switch (lane_prtcl) { 730 case SGMII_FM1_DTSEC1: 731 case SGMII_FM1_DTSEC2: 732 case SGMII_FM1_DTSEC3: 733 case SGMII_FM1_DTSEC4: 734 case SGMII_FM2_DTSEC1: 735 case SGMII_FM2_DTSEC2: 736 case SGMII_FM2_DTSEC3: 737 case SGMII_FM2_DTSEC4: 738 case SGMII_FM2_DTSEC5: 739 case XAUI_FM1: 740 case XAUI_FM2: 741 case SRIO1: 742 case SRIO2: 743 case AURORA: 744 out_be32(&srds_regs->lane[idx].ttlcr0, 745 SRDS_TTLCR0_FLT_SEL_KFR_26 | 746 SRDS_TTLCR0_FLT_SEL_KPH_28 | 747 SRDS_TTLCR0_FLT_SEL_750PPM | 748 SRDS_TTLCR0_FREQOVD_EN); 749 break; 750 default: 751 break; 752 } 753 #endif 754 755 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 756 switch (lane_prtcl) { 757 case PCIE1: 758 case PCIE2: 759 case PCIE3: 760 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >> 761 (lane_prtcl - PCIE1); 762 break; 763 case SRIO1: 764 case SRIO2: 765 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >> 766 (lane_prtcl - SRIO1); 767 break; 768 case SGMII_FM1_DTSEC1: 769 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 770 FSL_CORENET_DEVDISR2_DTSEC1_1; 771 break; 772 case SGMII_FM1_DTSEC2: 773 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 774 FSL_CORENET_DEVDISR2_DTSEC1_2; 775 break; 776 case SGMII_FM1_DTSEC3: 777 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 778 FSL_CORENET_DEVDISR2_DTSEC1_3; 779 break; 780 case SGMII_FM1_DTSEC4: 781 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 782 FSL_CORENET_DEVDISR2_DTSEC1_4; 783 break; 784 case SGMII_FM2_DTSEC1: 785 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 786 FSL_CORENET_DEVDISR2_DTSEC2_1; 787 break; 788 case SGMII_FM2_DTSEC2: 789 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 790 FSL_CORENET_DEVDISR2_DTSEC2_2; 791 break; 792 case SGMII_FM2_DTSEC3: 793 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 794 FSL_CORENET_DEVDISR2_DTSEC2_3; 795 break; 796 case SGMII_FM2_DTSEC4: 797 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 798 FSL_CORENET_DEVDISR2_DTSEC2_4; 799 break; 800 case SGMII_FM2_DTSEC5: 801 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 802 FSL_CORENET_DEVDISR2_DTSEC2_5; 803 break; 804 case XAUI_FM1: 805 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 806 FSL_CORENET_DEVDISR2_10GEC1; 807 break; 808 case XAUI_FM2: 809 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 810 FSL_CORENET_DEVDISR2_10GEC2; 811 break; 812 case AURORA: 813 break; 814 default: 815 break; 816 } 817 818 #endif 819 } 820 #endif 821 822 #ifdef DEBUG 823 puts("\n"); 824 #endif 825 826 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 827 p4080_erratum_serdes_a005(srds_regs, cfg); 828 #endif 829 830 for (idx = 0; idx < SRDS_MAX_BANK; idx++) { 831 bank = idx; 832 833 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 834 /* 835 * Change bank init order to 0, 2, 1, so that the third bank's 836 * PLL is established before we start the second bank. The 837 * second bank uses the third bank's PLL. 838 */ 839 840 if (idx == 1) 841 bank = FSL_SRDS_BANK_3; 842 else if (idx == 2) 843 bank = FSL_SRDS_BANK_2; 844 #endif 845 846 /* Skip disabled banks */ 847 if (!have_bank[bank]) 848 continue; 849 850 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 851 if (idx == 1) { 852 /* 853 * Re-enable devices on banks two and three that were 854 * disabled by the RCW, and then enable bank three. The 855 * devices need to be enabled before either bank is 856 * powered up. 857 */ 858 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr, 859 serdes8_devdisr2, cfg); 860 } else if (idx == 2) { 861 /* Enable bank two now that bank three is enabled. */ 862 enable_bank(gur, FSL_SRDS_BANK_2); 863 } 864 #endif 865 866 wait_for_rstdone(bank); 867 } 868 869 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 870 if (need_serdes_a001) { 871 /* Bank 3 has been enabled, so now we can disable bank 2 */ 872 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, 873 SRDS_RSTCTL_SDPD); 874 } 875 #endif 876 } 877