1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 25 #include <hwconfig.h> 26 #endif 27 #include <asm/fsl_serdes.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/io.h> 30 #include <asm/processor.h> 31 #include <asm/fsl_law.h> 32 #include "fsl_corenet_serdes.h" 33 34 static u32 serdes_prtcl_map; 35 36 #define HWCONFIG_BUFFER_SIZE 128 37 38 #ifdef DEBUG 39 static const char *serdes_prtcl_str[] = { 40 [NONE] = "NA", 41 [PCIE1] = "PCIE1", 42 [PCIE2] = "PCIE2", 43 [PCIE3] = "PCIE3", 44 [PCIE4] = "PCIE4", 45 [SATA1] = "SATA1", 46 [SATA2] = "SATA2", 47 [SRIO1] = "SRIO1", 48 [SRIO2] = "SRIO2", 49 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", 50 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", 51 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", 52 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", 53 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", 54 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", 55 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", 56 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", 57 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", 58 [XAUI_FM1] = "XAUI_FM1", 59 [XAUI_FM2] = "XAUI_FM2", 60 [AURORA] = "DEBUG", 61 }; 62 #endif 63 64 static const struct { 65 int idx; 66 unsigned int lpd; /* RCW lane powerdown bit */ 67 int bank; 68 } lanes[SRDS_MAX_LANES] = { 69 { 0, 152, FSL_SRDS_BANK_1 }, 70 { 1, 153, FSL_SRDS_BANK_1 }, 71 { 2, 154, FSL_SRDS_BANK_1 }, 72 { 3, 155, FSL_SRDS_BANK_1 }, 73 { 4, 156, FSL_SRDS_BANK_1 }, 74 { 5, 157, FSL_SRDS_BANK_1 }, 75 { 6, 158, FSL_SRDS_BANK_1 }, 76 { 7, 159, FSL_SRDS_BANK_1 }, 77 { 8, 160, FSL_SRDS_BANK_1 }, 78 { 9, 161, FSL_SRDS_BANK_1 }, 79 { 16, 162, FSL_SRDS_BANK_2 }, 80 { 17, 163, FSL_SRDS_BANK_2 }, 81 { 18, 164, FSL_SRDS_BANK_2 }, 82 { 19, 165, FSL_SRDS_BANK_2 }, 83 { 20, 170, FSL_SRDS_BANK_3 }, 84 { 21, 171, FSL_SRDS_BANK_3 }, 85 { 22, 172, FSL_SRDS_BANK_3 }, 86 { 23, 173, FSL_SRDS_BANK_3 }, 87 }; 88 89 int serdes_get_lane_idx(int lane) 90 { 91 return lanes[lane].idx; 92 } 93 94 int serdes_get_bank(int lane) 95 { 96 return lanes[lane].bank; 97 } 98 99 int serdes_lane_enabled(int lane) 100 { 101 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 102 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 103 104 int bank = lanes[lane].bank; 105 int word = lanes[lane].lpd / 32; 106 int bit = lanes[lane].lpd % 32; 107 108 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) 109 return 0; 110 111 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 112 /* 113 * For banks two and three, use the srds_lpd_b[] array instead of the 114 * RCW, because this array contains the real values of SRDS_LPD_B2 and 115 * SRDS_LPD_B3. 116 */ 117 if (bank > 0) 118 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); 119 #endif 120 121 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); 122 } 123 124 int is_serdes_configured(enum srds_prtcl device) 125 { 126 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 127 128 /* Is serdes enabled at all? */ 129 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 130 return 0; 131 132 return (1 << device) & serdes_prtcl_map; 133 } 134 135 #ifndef CONFIG_SYS_DCSRBAR_PHYS 136 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ 137 #define CONFIG_SYS_DCSRBAR 0x80000000 138 #define __DCSR_NOT_DEFINED_BY_CONFIG 139 #endif 140 141 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 142 static void enable_bank(ccsr_gur_t *gur, int bank) 143 { 144 u32 rcw5; 145 146 /* 147 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in 148 * CCSR, and read/write in DSCR. 149 */ 150 rcw5 = in_be32(gur->rcwsr + 5); 151 if (bank == FSL_SRDS_BANK_2) { 152 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2; 153 rcw5 |= srds_lpd_b[bank] << 26; 154 } else if (bank == FSL_SRDS_BANK_3) { 155 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3; 156 rcw5 |= srds_lpd_b[bank] << 18; 157 } else { 158 printf("SERDES: enable_bank: bad bank %d\n", bank + 1); 159 return; 160 } 161 162 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation 163 * of the DCSR mapping. 164 */ 165 { 166 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 167 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); 168 int law_index; 169 if (law.index == -1) 170 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, 171 LAW_SIZE_1M, LAW_TRGT_IF_DCSR); 172 else 173 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, 174 LAW_TRGT_IF_DCSR); 175 #endif 176 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; 177 out_be32(p, rcw5); 178 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 179 if (law.index == -1) 180 disable_law(law_index); 181 else 182 set_law(law.index, law.addr, law.size, law.trgt_id); 183 #endif 184 } 185 } 186 187 /* 188 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from 189 * bank 3 to clock banks 2 and 3, as well as a limited selection of 190 * protocol configurations. This requires that banks 2 and 3's lanes be 191 * disabled in the RCW, and enabled with some fixup here to re-enable 192 * them, and to configure bank 2's clock parameters in bank 3's pll in 193 * cases where they differ. 194 */ 195 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, 196 u32 devdisr, u32 devdisr2, int cfg) 197 { 198 int srds_ratio_b2; 199 int rfck_sel; 200 201 /* 202 * The disabled lanes of bank 2 will cause the associated 203 * logic blocks to be disabled in DEVDISR. We reverse that here. 204 * 205 * Note that normally it is not permitted to clear DEVDISR bits 206 * once the device has been disabled, but the hardware people 207 * say that this special case is OK. 208 */ 209 clrbits_be32(&gur->devdisr, devdisr); 210 clrbits_be32(&gur->devdisr2, devdisr2); 211 212 /* 213 * Some protocols require special handling. There are a few 214 * additional protocol configurations that can be used, which are 215 * not listed here. See app note 4065 for supported protocol 216 * configurations. 217 */ 218 switch (cfg) { 219 case 0x19: 220 /* 221 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL. 222 * SGMII on bank 3 should still be usable. 223 */ 224 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, 225 SRDS_PLLCR1_PLL_BWSEL); 226 227 enable_bank(gur, FSL_SRDS_BANK_3); 228 break; 229 230 case 0x0f: 231 case 0x10: 232 /* 233 * Banks 2 (XAUI) and 3 (SGMII) have different clocking 234 * requirements in these configurations. Bank 3 cannot 235 * be used and should have its lanes (but not the bank 236 * itself) disabled in the RCW. We set up bank 3's pll 237 * for bank 2's needs here. 238 */ 239 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7; 240 241 /* Determine refclock from XAUI ratio */ 242 switch (srds_ratio_b2) { 243 case 1: /* 20:1 */ 244 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25; 245 break; 246 case 2: /* 25:1 */ 247 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125; 248 break; 249 default: 250 printf("SERDES: bad SRDS_RATIO_B2 %d\n", 251 srds_ratio_b2); 252 return; 253 } 254 255 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 256 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel); 257 258 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 259 SRDS_PLLCR0_FRATE_SEL_MASK, 260 SRDS_PLLCR0_FRATE_SEL_6_25); 261 break; 262 default: 263 enable_bank(gur, FSL_SRDS_BANK_3); 264 } 265 266 } 267 #endif 268 269 void fsl_serdes_init(void) 270 { 271 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 272 int cfg; 273 serdes_corenet_t *srds_regs; 274 int lane, bank, idx; 275 enum srds_prtcl lane_prtcl; 276 long long end_tick; 277 int have_bank[SRDS_MAX_BANK] = {}; 278 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 279 u32 serdes8_devdisr = 0; 280 u32 serdes8_devdisr2 = 0; 281 char srds_lpd_opt[16]; 282 const char *srds_lpd_arg; 283 size_t arglen; 284 #endif 285 char buffer[HWCONFIG_BUFFER_SIZE]; 286 char *buf = NULL; 287 288 /* 289 * Extract hwconfig from environment since we have not properly setup 290 * the environment but need it for ddr config params 291 */ 292 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) 293 buf = buffer; 294 295 /* Is serdes enabled at all? */ 296 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 297 return; 298 299 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); 300 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 301 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg); 302 303 if (!is_serdes_prtcl_valid(cfg)) { 304 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg); 305 return; 306 } 307 308 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 309 /* 310 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3 311 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds 312 * for a description of these options. 313 */ 314 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { 315 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); 316 srds_lpd_arg = 317 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf); 318 if (srds_lpd_arg) 319 srds_lpd_b[bank] = 320 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf; 321 } 322 #endif 323 324 /* Look for banks with all lanes disabled, and power down the bank. */ 325 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 326 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); 327 if (serdes_lane_enabled(lane)) { 328 have_bank[serdes_get_bank(lane)] = 1; 329 serdes_prtcl_map |= (1 << lane_prtcl); 330 } 331 } 332 333 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 334 /* 335 * Bank two uses the clock from bank three, so if bank two is enabled, 336 * then bank three must also be enabled. 337 */ 338 if (have_bank[FSL_SRDS_BANK_2]) 339 have_bank[FSL_SRDS_BANK_3] = 1; 340 #endif 341 342 for (bank = 0; bank < SRDS_MAX_BANK; bank++) { 343 if (!have_bank[bank]) { 344 printf("SERDES: bank %d disabled\n", bank + 1); 345 setbits_be32(&srds_regs->bank[bank].rstctl, 346 SRDS_RSTCTL_SDPD); 347 } 348 } 349 350 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 351 idx = serdes_get_lane_idx(lane); 352 lane_prtcl = serdes_get_prtcl(cfg, lane); 353 354 #ifdef DEBUG 355 switch (lane) { 356 case 0: 357 puts("Bank1: "); 358 break; 359 case 10: 360 puts("\nBank2: "); 361 break; 362 case 14: 363 puts("\nBank3: "); 364 break; 365 default: 366 break; 367 } 368 369 printf("%s ", serdes_prtcl_str[lane_prtcl]); 370 #endif 371 372 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 373 switch (lane_prtcl) { 374 case PCIE1: 375 case PCIE2: 376 case PCIE3: 377 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >> 378 (lane_prtcl - PCIE1); 379 break; 380 case SRIO1: 381 case SRIO2: 382 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >> 383 (lane_prtcl - SRIO1); 384 break; 385 case SGMII_FM1_DTSEC1: 386 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 387 FSL_CORENET_DEVDISR2_DTSEC1_1; 388 break; 389 case SGMII_FM1_DTSEC2: 390 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 391 FSL_CORENET_DEVDISR2_DTSEC1_2; 392 break; 393 case SGMII_FM1_DTSEC3: 394 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 395 FSL_CORENET_DEVDISR2_DTSEC1_3; 396 break; 397 case SGMII_FM1_DTSEC4: 398 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 399 FSL_CORENET_DEVDISR2_DTSEC1_4; 400 break; 401 case SGMII_FM2_DTSEC1: 402 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 403 FSL_CORENET_DEVDISR2_DTSEC2_1; 404 break; 405 case SGMII_FM2_DTSEC2: 406 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 407 FSL_CORENET_DEVDISR2_DTSEC2_2; 408 break; 409 case SGMII_FM2_DTSEC3: 410 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 411 FSL_CORENET_DEVDISR2_DTSEC2_3; 412 break; 413 case SGMII_FM2_DTSEC4: 414 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 415 FSL_CORENET_DEVDISR2_DTSEC2_4; 416 break; 417 case XAUI_FM1: 418 case XAUI_FM2: 419 if (lane_prtcl == XAUI_FM1) 420 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 421 FSL_CORENET_DEVDISR2_10GEC1; 422 else 423 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 424 FSL_CORENET_DEVDISR2_10GEC2; 425 break; 426 case AURORA: 427 break; 428 default: 429 break; 430 } 431 432 #endif 433 } 434 435 #ifdef DEBUG 436 puts("\n"); 437 #endif 438 439 for (idx = 0; idx < SRDS_MAX_BANK; idx++) { 440 u32 rstctl; 441 442 bank = idx; 443 444 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 445 /* 446 * Change bank init order to 0, 2, 1, so that the third bank's 447 * PLL is established before we start the second bank. The 448 * second bank uses the third bank's PLL. 449 */ 450 451 if (idx == 1) 452 bank = FSL_SRDS_BANK_3; 453 else if (idx == 2) 454 bank = FSL_SRDS_BANK_2; 455 #endif 456 457 /* Skip disabled banks */ 458 if (!have_bank[bank]) 459 continue; 460 461 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 462 if (idx == 1) { 463 /* 464 * Re-enable devices on banks two and three that were 465 * disabled by the RCW, and then enable bank three. The 466 * devices need to be enabled before either bank is 467 * powered up. 468 */ 469 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr, 470 serdes8_devdisr2, cfg); 471 } else if (idx == 2) { 472 /* Eable bank two now that bank three is enabled. */ 473 enable_bank(gur, FSL_SRDS_BANK_2); 474 } 475 #endif 476 477 /* reset banks for errata */ 478 setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST); 479 480 /* wait for reset complete or 1-second timeout */ 481 end_tick = usec2ticks(1000000) + get_ticks(); 482 do { 483 rstctl = in_be32(&srds_regs->bank[bank].rstctl); 484 if (rstctl & SRDS_RSTCTL_RSTDONE) 485 break; 486 } while (end_tick > get_ticks()); 487 488 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) { 489 printf("SERDES: timeout resetting bank %d\n", 490 bank + 1); 491 continue; 492 } 493 } 494 } 495