1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 25 #include <hwconfig.h> 26 #endif 27 #include <asm/fsl_serdes.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/io.h> 30 #include <asm/processor.h> 31 #include <asm/fsl_law.h> 32 #include <asm/errno.h> 33 #include "fsl_corenet_serdes.h" 34 35 /* 36 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together. 37 * The code is already very complicated as it is, and separating the two 38 * completely would just make things worse. We try to keep them as separate 39 * as possible, but for now we require SERDES8 if SERDES_A001 is defined. 40 */ 41 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 42 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8 43 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8" 44 #endif 45 #endif 46 47 static u32 serdes_prtcl_map; 48 49 #define HWCONFIG_BUFFER_SIZE 128 50 51 #ifdef DEBUG 52 static const char *serdes_prtcl_str[] = { 53 [NONE] = "NA", 54 [PCIE1] = "PCIE1", 55 [PCIE2] = "PCIE2", 56 [PCIE3] = "PCIE3", 57 [PCIE4] = "PCIE4", 58 [SATA1] = "SATA1", 59 [SATA2] = "SATA2", 60 [SRIO1] = "SRIO1", 61 [SRIO2] = "SRIO2", 62 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", 63 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", 64 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", 65 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", 66 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", 67 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", 68 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", 69 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", 70 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", 71 [XAUI_FM1] = "XAUI_FM1", 72 [XAUI_FM2] = "XAUI_FM2", 73 [AURORA] = "DEBUG", 74 }; 75 #endif 76 77 static const struct { 78 int idx; 79 unsigned int lpd; /* RCW lane powerdown bit */ 80 int bank; 81 } lanes[SRDS_MAX_LANES] = { 82 { 0, 152, FSL_SRDS_BANK_1 }, 83 { 1, 153, FSL_SRDS_BANK_1 }, 84 { 2, 154, FSL_SRDS_BANK_1 }, 85 { 3, 155, FSL_SRDS_BANK_1 }, 86 { 4, 156, FSL_SRDS_BANK_1 }, 87 { 5, 157, FSL_SRDS_BANK_1 }, 88 { 6, 158, FSL_SRDS_BANK_1 }, 89 { 7, 159, FSL_SRDS_BANK_1 }, 90 { 8, 160, FSL_SRDS_BANK_1 }, 91 { 9, 161, FSL_SRDS_BANK_1 }, 92 { 16, 162, FSL_SRDS_BANK_2 }, 93 { 17, 163, FSL_SRDS_BANK_2 }, 94 { 18, 164, FSL_SRDS_BANK_2 }, 95 { 19, 165, FSL_SRDS_BANK_2 }, 96 { 20, 170, FSL_SRDS_BANK_3 }, 97 { 21, 171, FSL_SRDS_BANK_3 }, 98 { 22, 172, FSL_SRDS_BANK_3 }, 99 { 23, 173, FSL_SRDS_BANK_3 }, 100 }; 101 102 int serdes_get_lane_idx(int lane) 103 { 104 return lanes[lane].idx; 105 } 106 107 int serdes_get_bank_by_lane(int lane) 108 { 109 return lanes[lane].bank; 110 } 111 112 int serdes_lane_enabled(int lane) 113 { 114 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 115 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 116 117 int bank = lanes[lane].bank; 118 int word = lanes[lane].lpd / 32; 119 int bit = lanes[lane].lpd % 32; 120 121 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) 122 return 0; 123 124 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 125 /* 126 * For banks two and three, use the srds_lpd_b[] array instead of the 127 * RCW, because this array contains the real values of SRDS_LPD_B2 and 128 * SRDS_LPD_B3. 129 */ 130 if (bank > 0) 131 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); 132 #endif 133 134 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); 135 } 136 137 int is_serdes_configured(enum srds_prtcl device) 138 { 139 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 140 141 /* Is serdes enabled at all? */ 142 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 143 return 0; 144 145 return (1 << device) & serdes_prtcl_map; 146 } 147 148 static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device) 149 { 150 int i; 151 152 for (i = 0; i < SRDS_MAX_LANES; i++) { 153 if (serdes_get_prtcl(prtcl, i) == device) 154 return i; 155 } 156 157 return -ENODEV; 158 } 159 160 /* 161 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given 162 * device. This depends on the current SERDES protocol, as defined in the RCW. 163 * 164 * Returns a negative error code if SERDES is disabled or the given device is 165 * not supported in the current SERDES protocol. 166 */ 167 int serdes_get_first_lane(enum srds_prtcl device) 168 { 169 u32 prtcl; 170 const ccsr_gur_t *gur; 171 172 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; 173 174 /* Is serdes enabled at all? */ 175 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) 176 return -ENODEV; 177 178 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 179 180 return __serdes_get_first_lane(prtcl, device); 181 } 182 183 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 184 /* 185 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given 186 * SERDES protocol. 187 * 188 * Returns a negative error code if the given device is not supported for the 189 * given SERDES protocol. 190 */ 191 static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device) 192 { 193 int lane; 194 195 lane = __serdes_get_first_lane(prtcl, device); 196 if (unlikely(lane < 0)) 197 return lane; 198 199 return serdes_get_bank_by_lane(lane); 200 } 201 202 static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device, 203 int first) 204 { 205 int lane; 206 207 for (lane = first; lane < SRDS_MAX_LANES; lane++) { 208 if (serdes_get_prtcl(prtcl, lane) != device) 209 break; 210 } 211 212 return lane - first; 213 } 214 215 static void __serdes_reset_rx(serdes_corenet_t *regs, 216 uint32_t prtcl, 217 enum srds_prtcl device) 218 { 219 int lane, idx, first, last; 220 221 lane = __serdes_get_first_lane(prtcl, device); 222 if (unlikely(lane < 0)) 223 return; 224 first = serdes_get_lane_idx(lane); 225 last = first + __serdes_get_lane_count(prtcl, device, lane); 226 227 /* 228 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is 229 * selected as XAUI to place the lane into reset. 230 */ 231 for (idx = first; idx < last; idx++) 232 clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); 233 234 /* Wait at least 250 ns */ 235 udelay(1); 236 237 /* 238 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is 239 * selected as XAUI to bring the lane out of reset. 240 */ 241 for (idx = first; idx < last; idx++) 242 setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); 243 } 244 245 void serdes_reset_rx(enum srds_prtcl device) 246 { 247 u32 prtcl; 248 const ccsr_gur_t *gur; 249 serdes_corenet_t *regs; 250 251 if (unlikely(device == NONE)) 252 return; 253 254 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; 255 256 /* Is serdes enabled at all? */ 257 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) 258 return; 259 260 regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 261 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 262 263 __serdes_reset_rx(regs, prtcl, device); 264 } 265 #endif 266 267 #ifndef CONFIG_SYS_DCSRBAR_PHYS 268 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ 269 #define CONFIG_SYS_DCSRBAR 0x80000000 270 #define __DCSR_NOT_DEFINED_BY_CONFIG 271 #endif 272 273 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 274 /* 275 * Enable a SERDES bank that was disabled via the RCW 276 * 277 * We only call this function for SERDES8 and SERDES-A001 in cases we really 278 * want to enable the bank, whether we actually want to use the lanes or not, 279 * so make sure at least one lane is enabled. We're only enabling this one 280 * lane to satisfy errata requirements that the bank be enabled. 281 * 282 * We use a local variable instead of srds_lpd_b[] because we want drivers to 283 * think that the lanes actually are disabled. 284 */ 285 static void enable_bank(ccsr_gur_t *gur, int bank) 286 { 287 u32 rcw5; 288 u32 temp_lpd_b = srds_lpd_b[bank]; 289 290 /* 291 * If we're asked to disable all lanes, just pretend we're doing 292 * that. 293 */ 294 if (temp_lpd_b == 0xF) 295 temp_lpd_b = 0xE; 296 297 /* 298 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in 299 * CCSR, and read/write in DSCR. 300 */ 301 rcw5 = in_be32(gur->rcwsr + 5); 302 if (bank == FSL_SRDS_BANK_2) { 303 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2; 304 rcw5 |= temp_lpd_b << 26; 305 } else if (bank == FSL_SRDS_BANK_3) { 306 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3; 307 rcw5 |= temp_lpd_b << 18; 308 } else { 309 printf("SERDES: enable_bank: bad bank %d\n", bank + 1); 310 return; 311 } 312 313 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation 314 * of the DCSR mapping. 315 */ 316 { 317 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 318 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); 319 int law_index; 320 if (law.index == -1) 321 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, 322 LAW_SIZE_1M, LAW_TRGT_IF_DCSR); 323 else 324 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, 325 LAW_TRGT_IF_DCSR); 326 #endif 327 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; 328 out_be32(p, rcw5); 329 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 330 if (law.index == -1) 331 disable_law(law_index); 332 else 333 set_law(law.index, law.addr, law.size, law.trgt_id); 334 #endif 335 } 336 } 337 338 /* 339 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from 340 * bank 3 to clock banks 2 and 3, as well as a limited selection of 341 * protocol configurations. This requires that banks 2 and 3's lanes be 342 * disabled in the RCW, and enabled with some fixup here to re-enable 343 * them, and to configure bank 2's clock parameters in bank 3's pll in 344 * cases where they differ. 345 */ 346 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, 347 u32 devdisr, u32 devdisr2, int cfg) 348 { 349 int srds_ratio_b2; 350 int rfck_sel; 351 352 /* 353 * The disabled lanes of bank 2 will cause the associated 354 * logic blocks to be disabled in DEVDISR. We reverse that here. 355 * 356 * Note that normally it is not permitted to clear DEVDISR bits 357 * once the device has been disabled, but the hardware people 358 * say that this special case is OK. 359 */ 360 clrbits_be32(&gur->devdisr, devdisr); 361 clrbits_be32(&gur->devdisr2, devdisr2); 362 363 /* 364 * Some protocols require special handling. There are a few 365 * additional protocol configurations that can be used, which are 366 * not listed here. See app note 4065 for supported protocol 367 * configurations. 368 */ 369 switch (cfg) { 370 case 0x19: 371 /* 372 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL. 373 * SGMII on bank 3 should still be usable. 374 */ 375 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, 376 SRDS_PLLCR1_PLL_BWSEL); 377 break; 378 379 case 0x0f: 380 case 0x10: 381 /* 382 * Banks 2 (XAUI) and 3 (SGMII) have different clocking 383 * requirements in these configurations. Bank 3 cannot 384 * be used and should have its lanes (but not the bank 385 * itself) disabled in the RCW. We set up bank 3's pll 386 * for bank 2's needs here. 387 */ 388 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7; 389 390 /* Determine refclock from XAUI ratio */ 391 switch (srds_ratio_b2) { 392 case 1: /* 20:1 */ 393 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25; 394 break; 395 case 2: /* 25:1 */ 396 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125; 397 break; 398 default: 399 printf("SERDES: bad SRDS_RATIO_B2 %d\n", 400 srds_ratio_b2); 401 return; 402 } 403 404 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 405 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel); 406 407 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 408 SRDS_PLLCR0_FRATE_SEL_MASK, 409 SRDS_PLLCR0_FRATE_SEL_6_25); 410 break; 411 } 412 413 enable_bank(gur, FSL_SRDS_BANK_3); 414 } 415 #endif 416 417 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 418 /* 419 * If PCIe is not selected as a protocol for any lanes driven by a given PLL, 420 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0. 421 */ 422 static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) 423 { 424 enum srds_prtcl device; 425 426 switch (cfg) { 427 case 0x13: 428 case 0x16: 429 /* 430 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL] 431 * to 0. 432 */ 433 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, 434 SRDS_PLLCR1_PLL_BWSEL); 435 break; 436 case 0x19: 437 /* 438 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and 439 * SRDSB3PLLCR1[PLLBW_SEL] to 1. 440 */ 441 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, 442 SRDS_PLLCR1_PLL_BWSEL); 443 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, 444 SRDS_PLLCR1_PLL_BWSEL); 445 break; 446 } 447 448 /* 449 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI 450 * before XAUI is initialized. 451 */ 452 for (device = XAUI_FM1; device <= XAUI_FM2; device++) { 453 if (is_serdes_configured(device)) { 454 int bank = serdes_get_bank_by_device(cfg, device); 455 456 clrbits_be32(®s->bank[bank].pllcr1, 457 SRDS_PLLCR1_PLL_BWSEL); 458 } 459 } 460 } 461 #endif 462 463 /* 464 * Wait for the RSTDONE bit to get set, or a one-second timeout. 465 */ 466 static void wait_for_rstdone(unsigned int bank) 467 { 468 serdes_corenet_t *srds_regs = 469 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 470 unsigned long long end_tick; 471 u32 rstctl; 472 473 /* wait for reset complete or 1-second timeout */ 474 end_tick = usec2ticks(1000000) + get_ticks(); 475 do { 476 rstctl = in_be32(&srds_regs->bank[bank].rstctl); 477 if (rstctl & SRDS_RSTCTL_RSTDONE) 478 break; 479 } while (end_tick > get_ticks()); 480 481 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) 482 printf("SERDES: timeout resetting bank %u\n", bank + 1); 483 } 484 485 486 void __soc_serdes_init(void) 487 { 488 /* Allow for SoC-specific initialization in <SOC>_serdes.c */ 489 }; 490 void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init"))); 491 492 void fsl_serdes_init(void) 493 { 494 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 495 int cfg; 496 serdes_corenet_t *srds_regs; 497 int lane, bank, idx; 498 int have_bank[SRDS_MAX_BANK] = {}; 499 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 500 u32 serdes8_devdisr = 0; 501 u32 serdes8_devdisr2 = 0; 502 char srds_lpd_opt[16]; 503 const char *srds_lpd_arg; 504 size_t arglen; 505 #endif 506 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 507 int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ 508 #endif 509 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 510 char buffer[HWCONFIG_BUFFER_SIZE]; 511 char *buf = NULL; 512 513 /* 514 * Extract hwconfig from environment since we have not properly setup 515 * the environment but need it for ddr config params 516 */ 517 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) 518 buf = buffer; 519 #endif 520 521 /* Is serdes enabled at all? */ 522 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 523 return; 524 525 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); 526 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 527 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg); 528 529 if (!is_serdes_prtcl_valid(cfg)) { 530 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg); 531 return; 532 } 533 534 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 535 /* 536 * Display a warning if banks two and three are not disabled in the RCW, 537 * since our work-around for SERDES8 depends on these banks being 538 * disabled at power-on. 539 */ 540 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3) 541 if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) { 542 printf("Warning: SERDES8 requires banks two and " 543 "three to be disabled in the RCW\n"); 544 } 545 546 /* 547 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3 548 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds 549 * for a description of these options. 550 */ 551 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { 552 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); 553 srds_lpd_arg = 554 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf); 555 if (srds_lpd_arg) 556 srds_lpd_b[bank] = 557 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf; 558 } 559 560 if ((cfg == 0xf) || (cfg == 0x10)) { 561 /* 562 * For SERDES protocols 0xF and 0x10, force bank 3 to be 563 * disabled, because it is not supported. 564 */ 565 srds_lpd_b[FSL_SRDS_BANK_3] = 0xF; 566 } 567 #endif 568 569 /* Look for banks with all lanes disabled, and power down the bank. */ 570 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 571 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); 572 if (serdes_lane_enabled(lane)) { 573 have_bank[serdes_get_bank_by_lane(lane)] = 1; 574 serdes_prtcl_map |= (1 << lane_prtcl); 575 } 576 } 577 578 soc_serdes_init(); 579 580 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 581 /* 582 * Bank two uses the clock from bank three, so if bank two is enabled, 583 * then bank three must also be enabled. 584 */ 585 if (have_bank[FSL_SRDS_BANK_2]) 586 have_bank[FSL_SRDS_BANK_3] = 1; 587 #endif 588 589 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 590 /* 591 * The work-aroud for erratum SERDES-A001 is needed only if bank two 592 * is disabled and bank three is enabled. The converse is also true, 593 * but SERDES8 ensures that bank 3 is always enabled if bank 2 is 594 * enabled, so there's no point in complicating the code to handle 595 * that situation. 596 */ 597 need_serdes_a001 = 598 !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; 599 #endif 600 601 /* Power down the banks we're not interested in */ 602 for (bank = 0; bank < SRDS_MAX_BANK; bank++) { 603 if (!have_bank[bank]) { 604 printf("SERDES: bank %d disabled\n", bank + 1); 605 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 606 /* 607 * Erratum SERDES-A001 says bank two needs to be powered 608 * down after bank three is powered up, so don't power 609 * down bank two here. 610 */ 611 if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2)) 612 setbits_be32(&srds_regs->bank[bank].rstctl, 613 SRDS_RSTCTL_SDPD); 614 #else 615 setbits_be32(&srds_regs->bank[bank].rstctl, 616 SRDS_RSTCTL_SDPD); 617 #endif 618 } 619 } 620 621 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) 622 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 623 enum srds_prtcl lane_prtcl; 624 625 idx = serdes_get_lane_idx(lane); 626 lane_prtcl = serdes_get_prtcl(cfg, lane); 627 628 #ifdef DEBUG 629 switch (lane) { 630 case 0: 631 puts("Bank1: "); 632 break; 633 case 10: 634 puts("\nBank2: "); 635 break; 636 case 14: 637 puts("\nBank3: "); 638 break; 639 default: 640 break; 641 } 642 643 printf("%s ", serdes_prtcl_str[lane_prtcl]); 644 #endif 645 646 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 647 /* 648 * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for 649 * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or 650 * AURORA before the device is initialized. 651 */ 652 switch (lane_prtcl) { 653 case SGMII_FM1_DTSEC1: 654 case SGMII_FM1_DTSEC2: 655 case SGMII_FM1_DTSEC3: 656 case SGMII_FM1_DTSEC4: 657 case SGMII_FM2_DTSEC1: 658 case SGMII_FM2_DTSEC2: 659 case SGMII_FM2_DTSEC3: 660 case SGMII_FM2_DTSEC4: 661 case XAUI_FM1: 662 case XAUI_FM2: 663 case SRIO1: 664 case SRIO2: 665 case AURORA: 666 clrsetbits_be32(&srds_regs->lane[idx].ttlcr0, 667 SRDS_TTLCR0_FLT_SEL_MASK, 668 SRDS_TTLCR0_FLT_SEL_750PPM | 669 SRDS_TTLCR0_PM_DIS); 670 default: 671 break; 672 } 673 #endif 674 675 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 676 switch (lane_prtcl) { 677 case PCIE1: 678 case PCIE2: 679 case PCIE3: 680 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >> 681 (lane_prtcl - PCIE1); 682 break; 683 case SRIO1: 684 case SRIO2: 685 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >> 686 (lane_prtcl - SRIO1); 687 break; 688 case SGMII_FM1_DTSEC1: 689 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 690 FSL_CORENET_DEVDISR2_DTSEC1_1; 691 break; 692 case SGMII_FM1_DTSEC2: 693 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 694 FSL_CORENET_DEVDISR2_DTSEC1_2; 695 break; 696 case SGMII_FM1_DTSEC3: 697 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 698 FSL_CORENET_DEVDISR2_DTSEC1_3; 699 break; 700 case SGMII_FM1_DTSEC4: 701 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 702 FSL_CORENET_DEVDISR2_DTSEC1_4; 703 break; 704 case SGMII_FM2_DTSEC1: 705 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 706 FSL_CORENET_DEVDISR2_DTSEC2_1; 707 break; 708 case SGMII_FM2_DTSEC2: 709 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 710 FSL_CORENET_DEVDISR2_DTSEC2_2; 711 break; 712 case SGMII_FM2_DTSEC3: 713 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 714 FSL_CORENET_DEVDISR2_DTSEC2_3; 715 break; 716 case SGMII_FM2_DTSEC4: 717 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 718 FSL_CORENET_DEVDISR2_DTSEC2_4; 719 break; 720 case XAUI_FM1: 721 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 722 FSL_CORENET_DEVDISR2_10GEC1; 723 break; 724 case XAUI_FM2: 725 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 726 FSL_CORENET_DEVDISR2_10GEC2; 727 break; 728 case AURORA: 729 break; 730 default: 731 break; 732 } 733 734 #endif 735 } 736 #endif 737 738 #ifdef DEBUG 739 puts("\n"); 740 #endif 741 742 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 743 p4080_erratum_serdes_a005(srds_regs, cfg); 744 #endif 745 746 for (idx = 0; idx < SRDS_MAX_BANK; idx++) { 747 bank = idx; 748 749 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 750 /* 751 * Change bank init order to 0, 2, 1, so that the third bank's 752 * PLL is established before we start the second bank. The 753 * second bank uses the third bank's PLL. 754 */ 755 756 if (idx == 1) 757 bank = FSL_SRDS_BANK_3; 758 else if (idx == 2) 759 bank = FSL_SRDS_BANK_2; 760 #endif 761 762 /* Skip disabled banks */ 763 if (!have_bank[bank]) 764 continue; 765 766 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 767 if (idx == 1) { 768 /* 769 * Re-enable devices on banks two and three that were 770 * disabled by the RCW, and then enable bank three. The 771 * devices need to be enabled before either bank is 772 * powered up. 773 */ 774 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr, 775 serdes8_devdisr2, cfg); 776 } else if (idx == 2) { 777 /* Enable bank two now that bank three is enabled. */ 778 enable_bank(gur, FSL_SRDS_BANK_2); 779 } 780 #endif 781 782 wait_for_rstdone(bank); 783 } 784 785 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 786 if (need_serdes_a001) { 787 /* Bank 3 has been enabled, so now we can disable bank 2 */ 788 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, 789 SRDS_RSTCTL_SDPD); 790 } 791 #endif 792 } 793