1 /* 2 * Copyright 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 25 #include <hwconfig.h> 26 #endif 27 #include <asm/fsl_serdes.h> 28 #include <asm/immap_85xx.h> 29 #include <asm/io.h> 30 #include <asm/processor.h> 31 #include <asm/fsl_law.h> 32 #include "fsl_corenet_serdes.h" 33 34 static u32 serdes_prtcl_map; 35 36 #ifdef DEBUG 37 static const char *serdes_prtcl_str[] = { 38 [NONE] = "NA", 39 [PCIE1] = "PCIE1", 40 [PCIE2] = "PCIE2", 41 [PCIE3] = "PCIE3", 42 [PCIE4] = "PCIE4", 43 [SATA1] = "SATA1", 44 [SATA2] = "SATA2", 45 [SRIO1] = "SRIO1", 46 [SRIO2] = "SRIO2", 47 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", 48 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", 49 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", 50 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", 51 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", 52 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", 53 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", 54 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", 55 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", 56 [XAUI_FM1] = "XAUI_FM1", 57 [XAUI_FM2] = "XAUI_FM2", 58 [AURORA] = "DEBUG", 59 }; 60 #endif 61 62 static const struct { 63 int idx; 64 unsigned int lpd; /* RCW lane powerdown bit */ 65 int bank; 66 } lanes[SRDS_MAX_LANES] = { 67 { 0, 152, FSL_SRDS_BANK_1 }, 68 { 1, 153, FSL_SRDS_BANK_1 }, 69 { 2, 154, FSL_SRDS_BANK_1 }, 70 { 3, 155, FSL_SRDS_BANK_1 }, 71 { 4, 156, FSL_SRDS_BANK_1 }, 72 { 5, 157, FSL_SRDS_BANK_1 }, 73 { 6, 158, FSL_SRDS_BANK_1 }, 74 { 7, 159, FSL_SRDS_BANK_1 }, 75 { 8, 160, FSL_SRDS_BANK_1 }, 76 { 9, 161, FSL_SRDS_BANK_1 }, 77 { 16, 162, FSL_SRDS_BANK_2 }, 78 { 17, 163, FSL_SRDS_BANK_2 }, 79 { 18, 164, FSL_SRDS_BANK_2 }, 80 { 19, 165, FSL_SRDS_BANK_2 }, 81 { 20, 170, FSL_SRDS_BANK_3 }, 82 { 21, 171, FSL_SRDS_BANK_3 }, 83 { 22, 172, FSL_SRDS_BANK_3 }, 84 { 23, 173, FSL_SRDS_BANK_3 }, 85 }; 86 87 int serdes_get_lane_idx(int lane) 88 { 89 return lanes[lane].idx; 90 } 91 92 int serdes_get_bank(int lane) 93 { 94 return lanes[lane].bank; 95 } 96 97 int serdes_lane_enabled(int lane) 98 { 99 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 100 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 101 102 int bank = lanes[lane].bank; 103 int word = lanes[lane].lpd / 32; 104 int bit = lanes[lane].lpd % 32; 105 106 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) 107 return 0; 108 109 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 110 if (!IS_SVR_REV(get_svr(), 1, 0)) 111 if (bank > 0) 112 return !(srds_lpd_b[bank] & 113 (8 >> (lane - (6 + 4 * bank)))); 114 #endif 115 116 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); 117 } 118 119 int is_serdes_configured(enum srds_prtcl device) 120 { 121 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 122 123 /* Is serdes enabled at all? */ 124 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 125 return 0; 126 127 return (1 << device) & serdes_prtcl_map; 128 } 129 130 #ifndef CONFIG_SYS_DCSRBAR_PHYS 131 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ 132 #define CONFIG_SYS_DCSRBAR 0x80000000 133 #define __DCSR_NOT_DEFINED_BY_CONFIG 134 #endif 135 136 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 137 static void enable_bank(ccsr_gur_t *gur, int bank) 138 { 139 u32 rcw5; 140 141 /* 142 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in 143 * CCSR, and read/write in DSCR. 144 */ 145 rcw5 = in_be32(gur->rcwsr + 5); 146 if (bank == FSL_SRDS_BANK_2) { 147 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2; 148 rcw5 |= srds_lpd_b[bank] << 26; 149 } else if (bank == FSL_SRDS_BANK_3) { 150 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3; 151 rcw5 |= srds_lpd_b[bank] << 18; 152 } else { 153 printf("SERDES: enable_bank: bad bank %d\n", bank + 1); 154 return; 155 } 156 157 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation 158 * of the DCSR mapping. 159 */ 160 { 161 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 162 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); 163 int law_index; 164 if (law.index == -1) 165 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, 166 LAW_SIZE_1M, LAW_TRGT_IF_DCSR); 167 else 168 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, 169 LAW_TRGT_IF_DCSR); 170 #endif 171 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; 172 out_be32(p, rcw5); 173 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG 174 if (law.index == -1) 175 disable_law(law_index); 176 else 177 set_law(law.index, law.addr, law.size, law.trgt_id); 178 #endif 179 } 180 } 181 182 /* 183 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from 184 * bank 3 to clock banks 2 and 3, as well as a limited selection of 185 * protocol configurations. This requires that banks 2 and 3's lanes be 186 * disabled in the RCW, and enabled with some fixup here to re-enable 187 * them, and to configure bank 2's clock parameters in bank 3's pll in 188 * cases where they differ. 189 */ 190 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, 191 u32 devdisr, u32 devdisr2, int cfg) 192 { 193 int srds_ratio_b2; 194 int rfck_sel; 195 196 /* 197 * The disabled lanes of bank 2 will cause the associated 198 * logic blocks to be disabled in DEVDISR. We reverse that here. 199 * 200 * Note that normally it is not permitted to clear DEVDISR bits 201 * once the device has been disabled, but the hardware people 202 * say that this special case is OK. 203 */ 204 clrbits_be32(&gur->devdisr, devdisr); 205 clrbits_be32(&gur->devdisr2, devdisr2); 206 207 /* 208 * Some protocols require special handling. There are a few 209 * additional protocol configurations that can be used, which are 210 * not listed here. See app note 4065 for supported protocol 211 * configurations. 212 */ 213 switch (cfg) { 214 case 0x19: 215 /* 216 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL. 217 * SGMII on bank 3 should still be usable. 218 */ 219 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, 220 SRDS_PLLCR1_PLL_BWSEL); 221 222 enable_bank(gur, FSL_SRDS_BANK_3); 223 break; 224 225 case 0x0f: 226 case 0x10: 227 /* 228 * Banks 2 (XAUI) and 3 (SGMII) have different clocking 229 * requirements in these configurations. Bank 3 cannot 230 * be used and should have its lanes (but not the bank 231 * itself) disabled in the RCW. We set up bank 3's pll 232 * for bank 2's needs here. 233 */ 234 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7; 235 236 /* Determine refclock from XAUI ratio */ 237 switch (srds_ratio_b2) { 238 case 1: /* 20:1 */ 239 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25; 240 break; 241 case 2: /* 25:1 */ 242 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125; 243 break; 244 default: 245 printf("SERDES: bad SRDS_RATIO_B2 %d\n", 246 srds_ratio_b2); 247 return; 248 } 249 250 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 251 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel); 252 253 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, 254 SRDS_PLLCR0_FRATE_SEL_MASK, 255 SRDS_PLLCR0_FRATE_SEL_6_25); 256 break; 257 default: 258 enable_bank(gur, FSL_SRDS_BANK_3); 259 } 260 261 } 262 #endif 263 264 void fsl_serdes_init(void) 265 { 266 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 267 int cfg; 268 serdes_corenet_t *srds_regs; 269 int lane, bank, idx; 270 enum srds_prtcl lane_prtcl; 271 long long end_tick; 272 int have_bank[SRDS_MAX_BANK] = {}; 273 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 274 u32 serdes8_devdisr = 0; 275 u32 serdes8_devdisr2 = 0; 276 char srds_lpd_opt[16]; 277 const char *srds_lpd_arg; 278 size_t arglen; 279 #endif 280 281 /* Is serdes enabled at all? */ 282 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) 283 return; 284 285 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); 286 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 287 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg); 288 289 if (!is_serdes_prtcl_valid(cfg)) { 290 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg); 291 return; 292 } 293 294 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 295 if (!IS_SVR_REV(get_svr(), 1, 0)) 296 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { 297 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); 298 srds_lpd_arg = hwconfig_subarg("serdes", srds_lpd_opt, 299 &arglen); 300 if (srds_lpd_arg) 301 srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg, 302 NULL, 0); 303 } 304 #endif 305 306 /* Look for banks with all lanes disabled, and power down the bank. */ 307 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 308 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); 309 if (serdes_lane_enabled(lane)) { 310 have_bank[serdes_get_bank(lane)] = 1; 311 serdes_prtcl_map |= (1 << lane_prtcl); 312 } 313 } 314 315 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 316 if (IS_SVR_REV(get_svr(), 1, 0)) { 317 /* At least one bank must be disabled due to SERDES8. If 318 * no bank is found to be disabled based on lane 319 * disables, disable bank 3 because we can't turn off its 320 * lanes in the RCW without disabling MDIO due to erratum 321 * GEN8. 322 * 323 * This means that if you are relying on bank 3 being 324 * disabled to avoid SERDES8, in some cases you cannot 325 * also disable all lanes of another bank, or else bank 326 * 3 won't be disabled, leaving you with a configuration 327 * that isn't valid according to SERDES8 (e.g. if banks 328 * 2 and 3 have the same clock, and bank 1 is disabled 329 * instead of 3). 330 */ 331 for (bank = 0; bank < SRDS_MAX_BANK; bank++) { 332 if (!have_bank[bank]) 333 break; 334 } 335 336 if (bank == SRDS_MAX_BANK) 337 have_bank[FSL_SRDS_BANK_3] = 0; 338 } else { 339 if (have_bank[FSL_SRDS_BANK_2]) 340 have_bank[FSL_SRDS_BANK_3] = 1; 341 } 342 #endif 343 344 for (bank = 0; bank < SRDS_MAX_BANK; bank++) { 345 if (!have_bank[bank]) { 346 printf("SERDES: bank %d disabled\n", bank + 1); 347 setbits_be32(&srds_regs->bank[bank].rstctl, 348 SRDS_RSTCTL_SDPD); 349 } 350 } 351 352 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 353 idx = serdes_get_lane_idx(lane); 354 lane_prtcl = serdes_get_prtcl(cfg, lane); 355 356 #ifdef DEBUG 357 switch (lane) { 358 case 0: 359 puts("Bank1: "); 360 break; 361 case 10: 362 puts("\nBank2: "); 363 break; 364 case 14: 365 puts("\nBank3: "); 366 break; 367 default: 368 break; 369 } 370 371 printf("%s ", serdes_prtcl_str[lane_prtcl]); 372 #endif 373 374 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 375 switch (lane_prtcl) { 376 case PCIE1: 377 case PCIE2: 378 case PCIE3: 379 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >> 380 (lane_prtcl - PCIE1); 381 break; 382 case SRIO1: 383 case SRIO2: 384 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >> 385 (lane_prtcl - SRIO1); 386 break; 387 case SGMII_FM1_DTSEC1: 388 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 389 FSL_CORENET_DEVDISR2_DTSEC1_1; 390 break; 391 case SGMII_FM1_DTSEC2: 392 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 393 FSL_CORENET_DEVDISR2_DTSEC1_2; 394 break; 395 case SGMII_FM1_DTSEC3: 396 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 397 FSL_CORENET_DEVDISR2_DTSEC1_3; 398 break; 399 case SGMII_FM1_DTSEC4: 400 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 401 FSL_CORENET_DEVDISR2_DTSEC1_4; 402 break; 403 case SGMII_FM2_DTSEC1: 404 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 405 FSL_CORENET_DEVDISR2_DTSEC2_1; 406 break; 407 case SGMII_FM2_DTSEC2: 408 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 409 FSL_CORENET_DEVDISR2_DTSEC2_2; 410 break; 411 case SGMII_FM2_DTSEC3: 412 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 413 FSL_CORENET_DEVDISR2_DTSEC2_3; 414 break; 415 case SGMII_FM2_DTSEC4: 416 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 417 FSL_CORENET_DEVDISR2_DTSEC2_4; 418 break; 419 case XAUI_FM1: 420 case XAUI_FM2: 421 if (lane_prtcl == XAUI_FM1) 422 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | 423 FSL_CORENET_DEVDISR2_10GEC1; 424 else 425 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | 426 FSL_CORENET_DEVDISR2_10GEC2; 427 break; 428 case AURORA: 429 break; 430 default: 431 break; 432 } 433 434 #endif 435 } 436 437 #ifdef DEBUG 438 puts("\n"); 439 #endif 440 441 for (idx = 0; idx < SRDS_MAX_BANK; idx++) { 442 u32 rstctl; 443 444 bank = idx; 445 446 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 447 if (!IS_SVR_REV(get_svr(), 1, 0)) { 448 /* 449 * Change bank init order to 0, 2, 1, so that the 450 * third bank's PLL is established before we 451 * start the second bank which shares the third 452 * bank's PLL. 453 */ 454 455 if (idx == 1) 456 bank = FSL_SRDS_BANK_3; 457 else if (idx == 2) 458 bank = FSL_SRDS_BANK_2; 459 } 460 #endif 461 462 /* Skip disabled banks */ 463 if (!have_bank[bank]) 464 continue; 465 466 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 467 if (!IS_SVR_REV(get_svr(), 1, 0)) { 468 if (idx == 1) { 469 p4080_erratum_serdes8(srds_regs, gur, 470 serdes8_devdisr, 471 serdes8_devdisr2, cfg); 472 } else if (idx == 2) { 473 enable_bank(gur, FSL_SRDS_BANK_2); 474 } 475 } 476 #endif 477 478 /* reset banks for errata */ 479 setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST); 480 481 /* wait for reset complete or 1-second timeout */ 482 end_tick = usec2ticks(1000000) + get_ticks(); 483 do { 484 rstctl = in_be32(&srds_regs->bank[bank].rstctl); 485 if (rstctl & SRDS_RSTCTL_RSTDONE) 486 break; 487 } while (end_tick > get_ticks()); 488 489 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) { 490 printf("SERDES: timeout resetting bank %d\n", 491 bank + 1); 492 continue; 493 } 494 } 495 } 496