1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/fsl_serdes.h> 9 #include <asm/immap_85xx.h> 10 #include <asm/io.h> 11 #include <asm/processor.h> 12 #include <asm/fsl_law.h> 13 #include <asm/errno.h> 14 #include "fsl_corenet2_serdes.h" 15 16 #ifdef CONFIG_SYS_FSL_SRDS_1 17 static u64 serdes1_prtcl_map; 18 #endif 19 #ifdef CONFIG_SYS_FSL_SRDS_2 20 static u64 serdes2_prtcl_map; 21 #endif 22 #ifdef CONFIG_SYS_FSL_SRDS_3 23 static u64 serdes3_prtcl_map; 24 #endif 25 #ifdef CONFIG_SYS_FSL_SRDS_4 26 static u64 serdes4_prtcl_map; 27 #endif 28 29 #ifdef DEBUG 30 static const char *serdes_prtcl_str[] = { 31 [NONE] = "NA", 32 [PCIE1] = "PCIE1", 33 [PCIE2] = "PCIE2", 34 [PCIE3] = "PCIE3", 35 [PCIE4] = "PCIE4", 36 [SATA1] = "SATA1", 37 [SATA2] = "SATA2", 38 [SRIO1] = "SRIO1", 39 [SRIO2] = "SRIO2", 40 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", 41 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", 42 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", 43 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", 44 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", 45 [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6", 46 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", 47 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", 48 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", 49 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", 50 [XAUI_FM1] = "XAUI_FM1", 51 [XAUI_FM2] = "XAUI_FM2", 52 [AURORA] = "DEBUG", 53 [CPRI1] = "CPRI1", 54 [CPRI2] = "CPRI2", 55 [CPRI3] = "CPRI3", 56 [CPRI4] = "CPRI4", 57 [CPRI5] = "CPRI5", 58 [CPRI6] = "CPRI6", 59 [CPRI7] = "CPRI7", 60 [CPRI8] = "CPRI8", 61 [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9", 62 [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10", 63 [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9", 64 [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10", 65 [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9", 66 [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10", 67 [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9", 68 [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10", 69 [QSGMII_FM1_A] = "QSGMII_FM1_A", 70 [QSGMII_FM1_B] = "QSGMII_FM1_B", 71 [QSGMII_FM2_A] = "QSGMII_FM2_A", 72 [QSGMII_FM2_B] = "QSGMII_FM2_B", 73 [XFI_FM1_MAC9] = "XFI_FM1_MAC9", 74 [XFI_FM1_MAC10] = "XFI_FM1_MAC10", 75 [XFI_FM2_MAC9] = "XFI_FM2_MAC9", 76 [XFI_FM2_MAC10] = "XFI_FM2_MAC10", 77 [INTERLAKEN] = "INTERLAKEN", 78 [QSGMII_SW1_A] = "QSGMII_SW1_A", 79 [QSGMII_SW1_B] = "QSGMII_SW1_B", 80 }; 81 #endif 82 83 int is_serdes_configured(enum srds_prtcl device) 84 { 85 u64 ret = 0; 86 87 #ifdef CONFIG_SYS_FSL_SRDS_1 88 ret |= (1ULL << device) & serdes1_prtcl_map; 89 #endif 90 #ifdef CONFIG_SYS_FSL_SRDS_2 91 ret |= (1ULL << device) & serdes2_prtcl_map; 92 #endif 93 #ifdef CONFIG_SYS_FSL_SRDS_3 94 ret |= (1ULL << device) & serdes3_prtcl_map; 95 #endif 96 #ifdef CONFIG_SYS_FSL_SRDS_4 97 ret |= (1ULL << device) & serdes4_prtcl_map; 98 #endif 99 100 return !!ret; 101 } 102 103 int serdes_get_first_lane(u32 sd, enum srds_prtcl device) 104 { 105 const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 106 u32 cfg = in_be32(&gur->rcwsr[4]); 107 int i; 108 109 switch (sd) { 110 #ifdef CONFIG_SYS_FSL_SRDS_1 111 case FSL_SRDS_1: 112 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 113 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 114 break; 115 #endif 116 #ifdef CONFIG_SYS_FSL_SRDS_2 117 case FSL_SRDS_2: 118 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 119 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 120 break; 121 #endif 122 #ifdef CONFIG_SYS_FSL_SRDS_3 123 case FSL_SRDS_3: 124 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; 125 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; 126 break; 127 #endif 128 #ifdef CONFIG_SYS_FSL_SRDS_4 129 case FSL_SRDS_4: 130 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL; 131 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; 132 break; 133 #endif 134 default: 135 printf("invalid SerDes%d\n", sd); 136 break; 137 } 138 /* Is serdes enabled at all? */ 139 if (unlikely(cfg == 0)) 140 return -ENODEV; 141 142 for (i = 0; i < SRDS_MAX_LANES; i++) { 143 if (serdes_get_prtcl(sd, cfg, i) == device) 144 return i; 145 } 146 147 return -ENODEV; 148 } 149 150 #define BC3_SHIFT 9 151 #define DC3_SHIFT 6 152 #define FC3_SHIFT 0 153 #define BC2_SHIFT 19 154 #define DC2_SHIFT 16 155 #define FC2_SHIFT 10 156 #define BC1_SHIFT 29 157 #define DC1_SHIFT 26 158 #define FC1_SHIFT 20 159 #define BC_MASK 0x1 160 #define DC_MASK 0x7 161 #define FC_MASK 0x3F 162 163 #define FUSE_VAL_MASK 0x00000003 164 #define FUSE_VAL_SHIFT 30 165 #define CR0_DCBIAS_SHIFT 5 166 #define CR1_FCAP_SHIFT 15 167 #define CR1_BCAP_SHIFT 29 168 #define FCAP_MASK 0x001F8000 169 #define BCAP_MASK 0x20000000 170 #define BCAP_OVD_MASK 0x10000000 171 #define BYP_CAL_MASK 0x02000000 172 173 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) 174 { 175 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 176 u64 serdes_prtcl_map = 0; 177 u32 cfg; 178 int lane; 179 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 180 struct ccsr_sfp_regs __iomem *sfp_regs = 181 (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); 182 u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; 183 u32 bc_status, fc_status, dc_status, pll_sr2; 184 serdes_corenet_t __iomem *srds_regs = (void *)sd_addr; 185 u32 sfp_spfr0, sel; 186 #endif 187 188 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; 189 /* Is serdes enabled at all? */ 190 if (!cfg) { 191 printf("SERDES%d is not enabled\n", sd + 1); 192 return 0; 193 } 194 195 /* Erratum A-007186 196 * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0) 197 * The workaround requires factory pre-set SerDes calibration values to be 198 * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0) 199 * These values have been shown to work across the 200 * entire temperature range for all SerDes. These values are then written into 201 * the SerDes registers to calibrate the SerDes PLL. 202 * 203 * This workaround for the protocols and rates that only have the Ring VCO. 204 */ 205 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 206 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0); 207 debug("A007186: sfp_spfr0= %x\n", sfp_spfr0); 208 209 sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK; 210 211 if (sel == 0x01 || sel == 0x02) { 212 for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) { 213 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); 214 debug("A007186: pll_num=%x pllcr0=%x\n", 215 pll_num, pll_status); 216 /* STEP 1 */ 217 /* Read factory pre-set SerDes calibration values 218 * from fuse block(SFP scratch register-sfp_spfr0) 219 */ 220 switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) { 221 case SRDS_PLLCR0_FRATE_SEL_3_0: 222 case SRDS_PLLCR0_FRATE_SEL_3_072: 223 debug("A007186: 3.0/3.072 protocol rate\n"); 224 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK; 225 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK; 226 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK; 227 break; 228 case SRDS_PLLCR0_FRATE_SEL_3_125: 229 debug("A007186: 3.125 protocol rate\n"); 230 bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK; 231 dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK; 232 fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK; 233 break; 234 case SRDS_PLLCR0_FRATE_SEL_3_75: 235 debug("A007186: 3.75 protocol rate\n"); 236 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK; 237 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK; 238 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK; 239 break; 240 default: 241 continue; 242 } 243 244 /* STEP 2 */ 245 /* Write SRDSxPLLnCR1[11:16] = FC 246 * Write SRDSxPLLnCR1[2] = BC 247 */ 248 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); 249 pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) | 250 ((fc << CR1_FCAP_SHIFT) & FCAP_MASK)); 251 out_be32(&srds_regs->bank[pll_num].pllcr1, 252 (pll_cr_upd | pll_cr1)); 253 debug("A007186: pll_num=%x Updated PLLCR1=%x\n", 254 pll_num, (pll_cr_upd | pll_cr1)); 255 /* Write SRDSxPLLnCR0[24:26] = DC 256 */ 257 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); 258 out_be32(&srds_regs->bank[pll_num].pllcr0, 259 pll_cr0 | (dc << CR0_DCBIAS_SHIFT)); 260 debug("A007186: pll_num=%x, Updated PLLCR0=%x\n", 261 pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT))); 262 /* Write SRDSxPLLnCR1[3] = 1 263 * Write SRDSxPLLnCR1[6] = 1 264 */ 265 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); 266 pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK); 267 out_be32(&srds_regs->bank[pll_num].pllcr1, 268 (pll_cr_upd | pll_cr1)); 269 debug("A007186: pll_num=%x Updated PLLCR1=%x\n", 270 pll_num, (pll_cr_upd | pll_cr1)); 271 272 /* STEP 3 */ 273 /* Read the status Registers */ 274 /* Verify SRDSxPLLnSR2[8] = BC */ 275 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); 276 debug("A007186: pll_num=%x pllsr2=%x\n", 277 pll_num, pll_sr2); 278 bc_status = (pll_sr2 >> 23) & BC_MASK; 279 if (bc_status != bc) 280 debug("BC mismatch\n"); 281 fc_status = (pll_sr2 >> 16) & FC_MASK; 282 if (fc_status != fc) 283 debug("FC mismatch\n"); 284 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); 285 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 | 286 0x02000000); 287 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); 288 dc_status = (pll_sr2 >> 17) & DC_MASK; 289 if (dc_status != dc) 290 debug("DC mismatch\n"); 291 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); 292 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 & 293 0xfdffffff); 294 295 /* STEP 4 */ 296 /* Wait 750us to verify the PLL is locked 297 * by checking SRDSxPLLnCR0[8] = 1. 298 */ 299 udelay(750); 300 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); 301 debug("A007186: pll_num=%x pllcr0=%x\n", 302 pll_num, pll_status); 303 304 if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0) 305 printf("A007186 Serdes PLL not locked\n"); 306 else 307 debug("A007186 Serdes PLL locked\n"); 308 } 309 } 310 #endif 311 312 cfg >>= sd_prctl_shift; 313 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); 314 if (!is_serdes_prtcl_valid(sd, cfg)) 315 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); 316 317 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 318 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); 319 serdes_prtcl_map |= (1ULL << lane_prtcl); 320 } 321 322 return serdes_prtcl_map; 323 } 324 325 void fsl_serdes_init(void) 326 { 327 328 #ifdef CONFIG_SYS_FSL_SRDS_1 329 serdes1_prtcl_map = serdes_init(FSL_SRDS_1, 330 CONFIG_SYS_FSL_CORENET_SERDES_ADDR, 331 FSL_CORENET2_RCWSR4_SRDS1_PRTCL, 332 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT); 333 #endif 334 #ifdef CONFIG_SYS_FSL_SRDS_2 335 serdes2_prtcl_map = serdes_init(FSL_SRDS_2, 336 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, 337 FSL_CORENET2_RCWSR4_SRDS2_PRTCL, 338 FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT); 339 #endif 340 #ifdef CONFIG_SYS_FSL_SRDS_3 341 serdes3_prtcl_map = serdes_init(FSL_SRDS_3, 342 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, 343 FSL_CORENET2_RCWSR4_SRDS3_PRTCL, 344 FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT); 345 #endif 346 #ifdef CONFIG_SYS_FSL_SRDS_4 347 serdes4_prtcl_map = serdes_init(FSL_SRDS_4, 348 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, 349 FSL_CORENET2_RCWSR4_SRDS4_PRTCL, 350 FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT); 351 #endif 352 353 } 354 355 const char *serdes_clock_to_string(u32 clock) 356 { 357 switch (clock) { 358 case SRDS_PLLCR0_RFCK_SEL_100: 359 return "100"; 360 case SRDS_PLLCR0_RFCK_SEL_125: 361 return "125"; 362 case SRDS_PLLCR0_RFCK_SEL_156_25: 363 return "156.25"; 364 case SRDS_PLLCR0_RFCK_SEL_161_13: 365 return "161.1328123"; 366 default: 367 #if defined(CONFIG_T4240QDS) 368 return "???"; 369 #else 370 return "122.88"; 371 #endif 372 } 373 } 374 375