1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/fsl_serdes.h> 9 #include <asm/immap_85xx.h> 10 #include <asm/io.h> 11 #include <asm/processor.h> 12 #include <asm/fsl_law.h> 13 #include <asm/errno.h> 14 #include "fsl_corenet2_serdes.h" 15 16 #ifdef CONFIG_SYS_FSL_SRDS_1 17 static u64 serdes1_prtcl_map; 18 #endif 19 #ifdef CONFIG_SYS_FSL_SRDS_2 20 static u64 serdes2_prtcl_map; 21 #endif 22 #ifdef CONFIG_SYS_FSL_SRDS_3 23 static u64 serdes3_prtcl_map; 24 #endif 25 #ifdef CONFIG_SYS_FSL_SRDS_4 26 static u64 serdes4_prtcl_map; 27 #endif 28 29 #ifdef DEBUG 30 static const char *serdes_prtcl_str[] = { 31 [NONE] = "NA", 32 [PCIE1] = "PCIE1", 33 [PCIE2] = "PCIE2", 34 [PCIE3] = "PCIE3", 35 [PCIE4] = "PCIE4", 36 [SATA1] = "SATA1", 37 [SATA2] = "SATA2", 38 [SRIO1] = "SRIO1", 39 [SRIO2] = "SRIO2", 40 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", 41 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", 42 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", 43 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", 44 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", 45 [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6", 46 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", 47 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", 48 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", 49 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", 50 [XAUI_FM1] = "XAUI_FM1", 51 [XAUI_FM2] = "XAUI_FM2", 52 [AURORA] = "DEBUG", 53 [CPRI1] = "CPRI1", 54 [CPRI2] = "CPRI2", 55 [CPRI3] = "CPRI3", 56 [CPRI4] = "CPRI4", 57 [CPRI5] = "CPRI5", 58 [CPRI6] = "CPRI6", 59 [CPRI7] = "CPRI7", 60 [CPRI8] = "CPRI8", 61 [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9", 62 [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10", 63 [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9", 64 [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10", 65 [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9", 66 [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10", 67 [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9", 68 [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10", 69 [QSGMII_FM1_A] = "QSGMII_FM1_A", 70 [QSGMII_FM1_B] = "QSGMII_FM1_B", 71 [QSGMII_FM2_A] = "QSGMII_FM2_A", 72 [QSGMII_FM2_B] = "QSGMII_FM2_B", 73 [XFI_FM1_MAC9] = "XFI_FM1_MAC9", 74 [XFI_FM1_MAC10] = "XFI_FM1_MAC10", 75 [XFI_FM2_MAC9] = "XFI_FM2_MAC9", 76 [XFI_FM2_MAC10] = "XFI_FM2_MAC10", 77 [INTERLAKEN] = "INTERLAKEN", 78 [QSGMII_SW1_A] = "QSGMII_SW1_A", 79 [QSGMII_SW1_B] = "QSGMII_SW1_B", 80 }; 81 #endif 82 83 int is_serdes_configured(enum srds_prtcl device) 84 { 85 u64 ret = 0; 86 87 #ifdef CONFIG_SYS_FSL_SRDS_1 88 ret |= (1ULL << device) & serdes1_prtcl_map; 89 #endif 90 #ifdef CONFIG_SYS_FSL_SRDS_2 91 ret |= (1ULL << device) & serdes2_prtcl_map; 92 #endif 93 #ifdef CONFIG_SYS_FSL_SRDS_3 94 ret |= (1ULL << device) & serdes3_prtcl_map; 95 #endif 96 #ifdef CONFIG_SYS_FSL_SRDS_4 97 ret |= (1ULL << device) & serdes4_prtcl_map; 98 #endif 99 100 return !!ret; 101 } 102 103 int serdes_get_first_lane(u32 sd, enum srds_prtcl device) 104 { 105 const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 106 u32 cfg = in_be32(&gur->rcwsr[4]); 107 int i; 108 109 switch (sd) { 110 #ifdef CONFIG_SYS_FSL_SRDS_1 111 case FSL_SRDS_1: 112 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 113 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 114 break; 115 #endif 116 #ifdef CONFIG_SYS_FSL_SRDS_2 117 case FSL_SRDS_2: 118 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 119 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 120 break; 121 #endif 122 #ifdef CONFIG_SYS_FSL_SRDS_3 123 case FSL_SRDS_3: 124 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; 125 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; 126 break; 127 #endif 128 #ifdef CONFIG_SYS_FSL_SRDS_4 129 case FSL_SRDS_4: 130 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL; 131 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; 132 break; 133 #endif 134 default: 135 printf("invalid SerDes%d\n", sd); 136 break; 137 } 138 /* Is serdes enabled at all? */ 139 if (unlikely(cfg == 0)) 140 return -ENODEV; 141 142 for (i = 0; i < SRDS_MAX_LANES; i++) { 143 if (serdes_get_prtcl(sd, cfg, i) == device) 144 return i; 145 } 146 147 return -ENODEV; 148 } 149 150 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) 151 { 152 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 153 u64 serdes_prtcl_map = 0; 154 u32 cfg; 155 int lane; 156 157 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; 158 /* Is serdes enabled at all? */ 159 if (!cfg) { 160 printf("SERDES%d is not enabled\n", sd + 1); 161 return 0; 162 } 163 164 cfg >>= sd_prctl_shift; 165 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); 166 if (!is_serdes_prtcl_valid(sd, cfg)) 167 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); 168 169 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 170 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); 171 serdes_prtcl_map |= (1ULL << lane_prtcl); 172 } 173 174 return serdes_prtcl_map; 175 } 176 177 void fsl_serdes_init(void) 178 { 179 180 #ifdef CONFIG_SYS_FSL_SRDS_1 181 serdes1_prtcl_map = serdes_init(FSL_SRDS_1, 182 CONFIG_SYS_FSL_CORENET_SERDES_ADDR, 183 FSL_CORENET2_RCWSR4_SRDS1_PRTCL, 184 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT); 185 #endif 186 #ifdef CONFIG_SYS_FSL_SRDS_2 187 serdes2_prtcl_map = serdes_init(FSL_SRDS_2, 188 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, 189 FSL_CORENET2_RCWSR4_SRDS2_PRTCL, 190 FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT); 191 #endif 192 #ifdef CONFIG_SYS_FSL_SRDS_3 193 serdes3_prtcl_map = serdes_init(FSL_SRDS_3, 194 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, 195 FSL_CORENET2_RCWSR4_SRDS3_PRTCL, 196 FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT); 197 #endif 198 #ifdef CONFIG_SYS_FSL_SRDS_4 199 serdes4_prtcl_map = serdes_init(FSL_SRDS_4, 200 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, 201 FSL_CORENET2_RCWSR4_SRDS4_PRTCL, 202 FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT); 203 #endif 204 205 } 206 207 const char *serdes_clock_to_string(u32 clock) 208 { 209 switch (clock) { 210 case SRDS_PLLCR0_RFCK_SEL_100: 211 return "100"; 212 case SRDS_PLLCR0_RFCK_SEL_125: 213 return "125"; 214 case SRDS_PLLCR0_RFCK_SEL_156_25: 215 return "156.25"; 216 case SRDS_PLLCR0_RFCK_SEL_161_13: 217 return "161.1328123"; 218 default: 219 #if defined(CONFIG_T4240QDS) 220 return "???"; 221 #else 222 return "122.88"; 223 #endif 224 } 225 } 226 227