1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/fsl_serdes.h> 9 #include <asm/immap_85xx.h> 10 #include <asm/io.h> 11 #include <asm/processor.h> 12 #include <asm/fsl_law.h> 13 #include <asm/errno.h> 14 #include <asm/fsl_errata.h> 15 #include "fsl_corenet2_serdes.h" 16 17 #ifdef CONFIG_SYS_FSL_SRDS_1 18 static u64 serdes1_prtcl_map; 19 #endif 20 #ifdef CONFIG_SYS_FSL_SRDS_2 21 static u64 serdes2_prtcl_map; 22 #endif 23 #ifdef CONFIG_SYS_FSL_SRDS_3 24 static u64 serdes3_prtcl_map; 25 #endif 26 #ifdef CONFIG_SYS_FSL_SRDS_4 27 static u64 serdes4_prtcl_map; 28 #endif 29 30 #ifdef DEBUG 31 static const char *serdes_prtcl_str[] = { 32 [NONE] = "NA", 33 [PCIE1] = "PCIE1", 34 [PCIE2] = "PCIE2", 35 [PCIE3] = "PCIE3", 36 [PCIE4] = "PCIE4", 37 [SATA1] = "SATA1", 38 [SATA2] = "SATA2", 39 [SRIO1] = "SRIO1", 40 [SRIO2] = "SRIO2", 41 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", 42 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", 43 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", 44 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", 45 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", 46 [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6", 47 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", 48 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", 49 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", 50 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", 51 [XAUI_FM1] = "XAUI_FM1", 52 [XAUI_FM2] = "XAUI_FM2", 53 [AURORA] = "DEBUG", 54 [CPRI1] = "CPRI1", 55 [CPRI2] = "CPRI2", 56 [CPRI3] = "CPRI3", 57 [CPRI4] = "CPRI4", 58 [CPRI5] = "CPRI5", 59 [CPRI6] = "CPRI6", 60 [CPRI7] = "CPRI7", 61 [CPRI8] = "CPRI8", 62 [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9", 63 [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10", 64 [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9", 65 [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10", 66 [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9", 67 [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10", 68 [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9", 69 [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10", 70 [QSGMII_FM1_A] = "QSGMII_FM1_A", 71 [QSGMII_FM1_B] = "QSGMII_FM1_B", 72 [QSGMII_FM2_A] = "QSGMII_FM2_A", 73 [QSGMII_FM2_B] = "QSGMII_FM2_B", 74 [XFI_FM1_MAC9] = "XFI_FM1_MAC9", 75 [XFI_FM1_MAC10] = "XFI_FM1_MAC10", 76 [XFI_FM2_MAC9] = "XFI_FM2_MAC9", 77 [XFI_FM2_MAC10] = "XFI_FM2_MAC10", 78 [INTERLAKEN] = "INTERLAKEN", 79 [QSGMII_SW1_A] = "QSGMII_SW1_A", 80 [QSGMII_SW1_B] = "QSGMII_SW1_B", 81 }; 82 #endif 83 84 int is_serdes_configured(enum srds_prtcl device) 85 { 86 u64 ret = 0; 87 88 #ifdef CONFIG_SYS_FSL_SRDS_1 89 ret |= (1ULL << device) & serdes1_prtcl_map; 90 #endif 91 #ifdef CONFIG_SYS_FSL_SRDS_2 92 ret |= (1ULL << device) & serdes2_prtcl_map; 93 #endif 94 #ifdef CONFIG_SYS_FSL_SRDS_3 95 ret |= (1ULL << device) & serdes3_prtcl_map; 96 #endif 97 #ifdef CONFIG_SYS_FSL_SRDS_4 98 ret |= (1ULL << device) & serdes4_prtcl_map; 99 #endif 100 101 return !!ret; 102 } 103 104 int serdes_get_first_lane(u32 sd, enum srds_prtcl device) 105 { 106 const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 107 u32 cfg = in_be32(&gur->rcwsr[4]); 108 int i; 109 110 switch (sd) { 111 #ifdef CONFIG_SYS_FSL_SRDS_1 112 case FSL_SRDS_1: 113 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 114 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 115 break; 116 #endif 117 #ifdef CONFIG_SYS_FSL_SRDS_2 118 case FSL_SRDS_2: 119 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 120 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 121 break; 122 #endif 123 #ifdef CONFIG_SYS_FSL_SRDS_3 124 case FSL_SRDS_3: 125 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; 126 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; 127 break; 128 #endif 129 #ifdef CONFIG_SYS_FSL_SRDS_4 130 case FSL_SRDS_4: 131 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL; 132 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; 133 break; 134 #endif 135 default: 136 printf("invalid SerDes%d\n", sd); 137 break; 138 } 139 /* Is serdes enabled at all? */ 140 if (unlikely(cfg == 0)) 141 return -ENODEV; 142 143 for (i = 0; i < SRDS_MAX_LANES; i++) { 144 if (serdes_get_prtcl(sd, cfg, i) == device) 145 return i; 146 } 147 148 return -ENODEV; 149 } 150 151 #define BC3_SHIFT 9 152 #define DC3_SHIFT 6 153 #define FC3_SHIFT 0 154 #define BC2_SHIFT 19 155 #define DC2_SHIFT 16 156 #define FC2_SHIFT 10 157 #define BC1_SHIFT 29 158 #define DC1_SHIFT 26 159 #define FC1_SHIFT 20 160 #define BC_MASK 0x1 161 #define DC_MASK 0x7 162 #define FC_MASK 0x3F 163 164 #define FUSE_VAL_MASK 0x00000003 165 #define FUSE_VAL_SHIFT 30 166 #define CR0_DCBIAS_SHIFT 5 167 #define CR1_FCAP_SHIFT 15 168 #define CR1_BCAP_SHIFT 29 169 #define FCAP_MASK 0x001F8000 170 #define BCAP_MASK 0x20000000 171 #define BCAP_OVD_MASK 0x10000000 172 #define BYP_CAL_MASK 0x02000000 173 174 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) 175 { 176 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 177 u64 serdes_prtcl_map = 0; 178 u32 cfg; 179 int lane; 180 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 181 struct ccsr_sfp_regs __iomem *sfp_regs = 182 (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); 183 u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; 184 u32 bc_status, fc_status, dc_status, pll_sr2; 185 serdes_corenet_t __iomem *srds_regs = (void *)sd_addr; 186 u32 sfp_spfr0, sel; 187 #endif 188 189 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; 190 191 /* Erratum A-007186 192 * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0) 193 * The workaround requires factory pre-set SerDes calibration values to be 194 * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0) 195 * These values have been shown to work across the 196 * entire temperature range for all SerDes. These values are then written into 197 * the SerDes registers to calibrate the SerDes PLL. 198 * 199 * This workaround for the protocols and rates that only have the Ring VCO. 200 */ 201 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 202 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0); 203 debug("A007186: sfp_spfr0= %x\n", sfp_spfr0); 204 205 sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK; 206 207 if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) { 208 for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) { 209 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); 210 debug("A007186: pll_num=%x pllcr0=%x\n", 211 pll_num, pll_status); 212 /* STEP 1 */ 213 /* Read factory pre-set SerDes calibration values 214 * from fuse block(SFP scratch register-sfp_spfr0) 215 */ 216 switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) { 217 case SRDS_PLLCR0_FRATE_SEL_3_0: 218 case SRDS_PLLCR0_FRATE_SEL_3_072: 219 debug("A007186: 3.0/3.072 protocol rate\n"); 220 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK; 221 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK; 222 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK; 223 break; 224 case SRDS_PLLCR0_FRATE_SEL_3_125: 225 debug("A007186: 3.125 protocol rate\n"); 226 bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK; 227 dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK; 228 fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK; 229 break; 230 case SRDS_PLLCR0_FRATE_SEL_3_75: 231 debug("A007186: 3.75 protocol rate\n"); 232 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK; 233 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK; 234 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK; 235 break; 236 default: 237 continue; 238 } 239 240 /* STEP 2 */ 241 /* Write SRDSxPLLnCR1[11:16] = FC 242 * Write SRDSxPLLnCR1[2] = BC 243 */ 244 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); 245 pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) | 246 ((fc << CR1_FCAP_SHIFT) & FCAP_MASK)); 247 out_be32(&srds_regs->bank[pll_num].pllcr1, 248 (pll_cr_upd | pll_cr1)); 249 debug("A007186: pll_num=%x Updated PLLCR1=%x\n", 250 pll_num, (pll_cr_upd | pll_cr1)); 251 /* Write SRDSxPLLnCR0[24:26] = DC 252 */ 253 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); 254 out_be32(&srds_regs->bank[pll_num].pllcr0, 255 pll_cr0 | (dc << CR0_DCBIAS_SHIFT)); 256 debug("A007186: pll_num=%x, Updated PLLCR0=%x\n", 257 pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT))); 258 /* Write SRDSxPLLnCR1[3] = 1 259 * Write SRDSxPLLnCR1[6] = 1 260 */ 261 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); 262 pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK); 263 out_be32(&srds_regs->bank[pll_num].pllcr1, 264 (pll_cr_upd | pll_cr1)); 265 debug("A007186: pll_num=%x Updated PLLCR1=%x\n", 266 pll_num, (pll_cr_upd | pll_cr1)); 267 268 /* STEP 3 */ 269 /* Read the status Registers */ 270 /* Verify SRDSxPLLnSR2[8] = BC */ 271 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); 272 debug("A007186: pll_num=%x pllsr2=%x\n", 273 pll_num, pll_sr2); 274 bc_status = (pll_sr2 >> 23) & BC_MASK; 275 if (bc_status != bc) 276 debug("BC mismatch\n"); 277 fc_status = (pll_sr2 >> 16) & FC_MASK; 278 if (fc_status != fc) 279 debug("FC mismatch\n"); 280 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); 281 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 | 282 0x02000000); 283 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); 284 dc_status = (pll_sr2 >> 17) & DC_MASK; 285 if (dc_status != dc) 286 debug("DC mismatch\n"); 287 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); 288 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 & 289 0xfdffffff); 290 291 /* STEP 4 */ 292 /* Wait 750us to verify the PLL is locked 293 * by checking SRDSxPLLnCR0[8] = 1. 294 */ 295 udelay(750); 296 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); 297 debug("A007186: pll_num=%x pllcr0=%x\n", 298 pll_num, pll_status); 299 300 if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0) 301 printf("A007186 Serdes PLL not locked\n"); 302 else 303 debug("A007186 Serdes PLL locked\n"); 304 } 305 } 306 #endif 307 308 cfg >>= sd_prctl_shift; 309 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); 310 if (!is_serdes_prtcl_valid(sd, cfg)) 311 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); 312 313 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 314 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); 315 serdes_prtcl_map |= (1ULL << lane_prtcl); 316 } 317 318 return serdes_prtcl_map; 319 } 320 321 void fsl_serdes_init(void) 322 { 323 324 #ifdef CONFIG_SYS_FSL_SRDS_1 325 serdes1_prtcl_map = serdes_init(FSL_SRDS_1, 326 CONFIG_SYS_FSL_CORENET_SERDES_ADDR, 327 FSL_CORENET2_RCWSR4_SRDS1_PRTCL, 328 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT); 329 #endif 330 #ifdef CONFIG_SYS_FSL_SRDS_2 331 serdes2_prtcl_map = serdes_init(FSL_SRDS_2, 332 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, 333 FSL_CORENET2_RCWSR4_SRDS2_PRTCL, 334 FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT); 335 #endif 336 #ifdef CONFIG_SYS_FSL_SRDS_3 337 serdes3_prtcl_map = serdes_init(FSL_SRDS_3, 338 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, 339 FSL_CORENET2_RCWSR4_SRDS3_PRTCL, 340 FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT); 341 #endif 342 #ifdef CONFIG_SYS_FSL_SRDS_4 343 serdes4_prtcl_map = serdes_init(FSL_SRDS_4, 344 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, 345 FSL_CORENET2_RCWSR4_SRDS4_PRTCL, 346 FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT); 347 #endif 348 349 } 350 351 const char *serdes_clock_to_string(u32 clock) 352 { 353 switch (clock) { 354 case SRDS_PLLCR0_RFCK_SEL_100: 355 return "100"; 356 case SRDS_PLLCR0_RFCK_SEL_125: 357 return "125"; 358 case SRDS_PLLCR0_RFCK_SEL_156_25: 359 return "156.25"; 360 case SRDS_PLLCR0_RFCK_SEL_161_13: 361 return "161.1328123"; 362 default: 363 #if defined(CONFIG_T4240QDS) 364 return "???"; 365 #else 366 return "122.88"; 367 #endif 368 } 369 } 370 371