1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <libfdt.h> 28 #include <fdt_support.h> 29 #include <asm/processor.h> 30 #include <linux/ctype.h> 31 #include <asm/io.h> 32 #include <asm/fsl_portals.h> 33 #ifdef CONFIG_FSL_ESDHC 34 #include <fsl_esdhc.h> 35 #endif 36 #include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 extern void ft_qe_setup(void *blob); 41 extern void ft_fixup_num_cores(void *blob); 42 extern void ft_srio_setup(void *blob); 43 44 #ifdef CONFIG_MP 45 #include "mp.h" 46 47 void ft_fixup_cpu(void *blob, u64 memory_limit) 48 { 49 int off; 50 phys_addr_t spin_tbl_addr = get_spin_phys_addr(); 51 u32 bootpg = determine_mp_bootpg(NULL); 52 u32 id = get_my_id(); 53 const char *enable_method; 54 55 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 56 while (off != -FDT_ERR_NOTFOUND) { 57 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 58 59 if (reg) { 60 u32 phys_cpu_id = thread_to_core(*reg); 61 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr; 62 val = cpu_to_fdt64(val); 63 if (*reg == id) { 64 fdt_setprop_string(blob, off, "status", 65 "okay"); 66 } else { 67 fdt_setprop_string(blob, off, "status", 68 "disabled"); 69 } 70 71 if (hold_cores_in_reset(0)) { 72 #ifdef CONFIG_FSL_CORENET 73 /* Cores held in reset, use BRR to release */ 74 enable_method = "fsl,brr-holdoff"; 75 #else 76 /* Cores held in reset, use EEBPCR to release */ 77 enable_method = "fsl,eebpcr-holdoff"; 78 #endif 79 } else { 80 /* Cores out of reset and in a spin-loop */ 81 enable_method = "spin-table"; 82 83 fdt_setprop(blob, off, "cpu-release-addr", 84 &val, sizeof(val)); 85 } 86 87 fdt_setprop_string(blob, off, "enable-method", 88 enable_method); 89 } else { 90 printf ("cpu NULL\n"); 91 } 92 off = fdt_node_offset_by_prop_value(blob, off, 93 "device_type", "cpu", 4); 94 } 95 96 /* Reserve the boot page so OSes dont use it */ 97 if ((u64)bootpg < memory_limit) { 98 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 99 if (off < 0) 100 printf("Failed to reserve memory for bootpg: %s\n", 101 fdt_strerror(off)); 102 } 103 /* Reserve spin table page */ 104 if (spin_tbl_addr < memory_limit) { 105 off = fdt_add_mem_rsv(blob, 106 (spin_tbl_addr & ~0xffful), 4096); 107 if (off < 0) 108 printf("Failed to reserve memory for spin table: %s\n", 109 fdt_strerror(off)); 110 } 111 } 112 #endif 113 114 #ifdef CONFIG_SYS_FSL_CPC 115 static inline void ft_fixup_l3cache(void *blob, int off) 116 { 117 u32 line_size, num_ways, size, num_sets; 118 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 119 u32 cfg0 = in_be32(&cpc->cpccfg0); 120 121 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 122 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 123 line_size = CPC_CFG0_LINE_SZ(cfg0); 124 num_sets = size / (line_size * num_ways); 125 126 fdt_setprop(blob, off, "cache-unified", NULL, 0); 127 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 128 fdt_setprop_cell(blob, off, "cache-size", size); 129 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 130 fdt_setprop_cell(blob, off, "cache-level", 3); 131 #ifdef CONFIG_SYS_CACHE_STASHING 132 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 133 #endif 134 } 135 #else 136 #define ft_fixup_l3cache(x, y) 137 #endif 138 139 #if defined(CONFIG_L2_CACHE) 140 /* return size in kilobytes */ 141 static inline u32 l2cache_size(void) 142 { 143 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 144 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 145 u32 ver = SVR_SOC_VER(get_svr()); 146 147 switch (l2siz_field) { 148 case 0x0: 149 break; 150 case 0x1: 151 if (ver == SVR_8540 || ver == SVR_8560 || 152 ver == SVR_8541 || ver == SVR_8555) 153 return 128; 154 else 155 return 256; 156 break; 157 case 0x2: 158 if (ver == SVR_8540 || ver == SVR_8560 || 159 ver == SVR_8541 || ver == SVR_8555) 160 return 256; 161 else 162 return 512; 163 break; 164 case 0x3: 165 return 1024; 166 break; 167 } 168 169 return 0; 170 } 171 172 static inline void ft_fixup_l2cache(void *blob) 173 { 174 int len, off; 175 u32 *ph; 176 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 177 178 const u32 line_size = 32; 179 const u32 num_ways = 8; 180 const u32 size = l2cache_size() * 1024; 181 const u32 num_sets = size / (line_size * num_ways); 182 183 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 184 if (off < 0) { 185 debug("no cpu node fount\n"); 186 return; 187 } 188 189 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 190 191 if (ph == NULL) { 192 debug("no next-level-cache property\n"); 193 return ; 194 } 195 196 off = fdt_node_offset_by_phandle(blob, *ph); 197 if (off < 0) { 198 printf("%s: %s\n", __func__, fdt_strerror(off)); 199 return ; 200 } 201 202 if (cpu) { 203 char buf[40]; 204 205 if (isdigit(cpu->name[0])) { 206 /* MPCxxxx, where xxxx == 4-digit number */ 207 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", 208 cpu->name) + 1; 209 } else { 210 /* Pxxxx or Txxxx, where xxxx == 4-digit number */ 211 len = sprintf(buf, "fsl,%c%s-l2-cache-controller", 212 tolower(cpu->name[0]), cpu->name + 1) + 1; 213 } 214 215 /* 216 * append "cache" after the NULL character that the previous 217 * sprintf wrote. This is how a device tree stores multiple 218 * strings in a property. 219 */ 220 len += sprintf(buf + len, "cache") + 1; 221 222 fdt_setprop(blob, off, "compatible", buf, len); 223 } 224 fdt_setprop(blob, off, "cache-unified", NULL, 0); 225 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 226 fdt_setprop_cell(blob, off, "cache-size", size); 227 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 228 fdt_setprop_cell(blob, off, "cache-level", 2); 229 230 /* we dont bother w/L3 since no platform of this type has one */ 231 } 232 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \ 233 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 234 static inline void ft_fixup_l2cache(void *blob) 235 { 236 int off, l2_off, l3_off = -1; 237 u32 *ph; 238 #ifdef CONFIG_BACKSIDE_L2_CACHE 239 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 240 #else 241 struct ccsr_cluster_l2 *l2cache = 242 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); 243 u32 l2cfg0 = in_be32(&l2cache->l2cfg0); 244 #endif 245 u32 size, line_size, num_ways, num_sets; 246 int has_l2 = 1; 247 248 /* P2040/P2040E has no L2, so dont set any L2 props */ 249 if (SVR_SOC_VER(get_svr()) == SVR_P2040) 250 has_l2 = 0; 251 252 size = (l2cfg0 & 0x3fff) * 64 * 1024; 253 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 254 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 255 num_sets = size / (line_size * num_ways); 256 257 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 258 259 while (off != -FDT_ERR_NOTFOUND) { 260 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 261 262 if (ph == NULL) { 263 debug("no next-level-cache property\n"); 264 goto next; 265 } 266 267 l2_off = fdt_node_offset_by_phandle(blob, *ph); 268 if (l2_off < 0) { 269 printf("%s: %s\n", __func__, fdt_strerror(off)); 270 goto next; 271 } 272 273 if (has_l2) { 274 #ifdef CONFIG_SYS_CACHE_STASHING 275 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 276 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 277 /* Only initialize every eighth thread */ 278 if (reg && !((*reg) % 8)) 279 #else 280 if (reg) 281 #endif 282 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 283 (*reg * 2) + 32 + 1); 284 #endif 285 286 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 287 fdt_setprop_cell(blob, l2_off, "cache-block-size", 288 line_size); 289 fdt_setprop_cell(blob, l2_off, "cache-size", size); 290 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 291 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 292 fdt_setprop(blob, l2_off, "compatible", "cache", 6); 293 } 294 295 if (l3_off < 0) { 296 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 297 298 if (ph == NULL) { 299 debug("no next-level-cache property\n"); 300 goto next; 301 } 302 l3_off = *ph; 303 } 304 next: 305 off = fdt_node_offset_by_prop_value(blob, off, 306 "device_type", "cpu", 4); 307 } 308 if (l3_off > 0) { 309 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 310 if (l3_off < 0) { 311 printf("%s: %s\n", __func__, fdt_strerror(off)); 312 return ; 313 } 314 ft_fixup_l3cache(blob, l3_off); 315 } 316 } 317 #else 318 #define ft_fixup_l2cache(x) 319 #endif 320 321 static inline void ft_fixup_cache(void *blob) 322 { 323 int off; 324 325 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 326 327 while (off != -FDT_ERR_NOTFOUND) { 328 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 329 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 330 u32 isize, iline_size, inum_sets, inum_ways; 331 u32 dsize, dline_size, dnum_sets, dnum_ways; 332 333 /* d-side config */ 334 dsize = (l1cfg0 & 0x7ff) * 1024; 335 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 336 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 337 dnum_sets = dsize / (dline_size * dnum_ways); 338 339 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 340 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 341 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 342 343 #ifdef CONFIG_SYS_CACHE_STASHING 344 { 345 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 346 if (reg) 347 fdt_setprop_cell(blob, off, "cache-stash-id", 348 (*reg * 2) + 32 + 0); 349 } 350 #endif 351 352 /* i-side config */ 353 isize = (l1cfg1 & 0x7ff) * 1024; 354 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 355 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 356 inum_sets = isize / (iline_size * inum_ways); 357 358 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 359 fdt_setprop_cell(blob, off, "i-cache-size", isize); 360 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 361 362 off = fdt_node_offset_by_prop_value(blob, off, 363 "device_type", "cpu", 4); 364 } 365 366 ft_fixup_l2cache(blob); 367 } 368 369 370 void fdt_add_enet_stashing(void *fdt) 371 { 372 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 373 374 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 375 376 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 377 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); 378 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); 379 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); 380 } 381 382 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 383 #ifdef CONFIG_SYS_DPAA_FMAN 384 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 385 unsigned long freq) 386 { 387 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 388 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 389 390 if (off >= 0) { 391 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 392 if (off > 0) 393 printf("WARNING enable to set clock-frequency " 394 "for %s: %s\n", compat, fdt_strerror(off)); 395 } 396 } 397 #endif 398 399 static void ft_fixup_dpaa_clks(void *blob) 400 { 401 sys_info_t sysinfo; 402 403 get_sys_info(&sysinfo); 404 #ifdef CONFIG_SYS_DPAA_FMAN 405 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 406 sysinfo.freqFMan[0]); 407 408 #if (CONFIG_SYS_NUM_FMAN == 2) 409 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 410 sysinfo.freqFMan[1]); 411 #endif 412 #endif 413 414 #ifdef CONFIG_SYS_DPAA_QBMAN 415 do_fixup_by_compat_u32(blob, "fsl,qman", 416 "clock-frequency", sysinfo.freqQMAN, 1); 417 #endif 418 419 #ifdef CONFIG_SYS_DPAA_PME 420 do_fixup_by_compat_u32(blob, "fsl,pme", 421 "clock-frequency", sysinfo.freqPME, 1); 422 #endif 423 } 424 #else 425 #define ft_fixup_dpaa_clks(x) 426 #endif 427 428 #ifdef CONFIG_QE 429 static void ft_fixup_qe_snum(void *blob) 430 { 431 unsigned int svr; 432 433 svr = mfspr(SPRN_SVR); 434 if (SVR_SOC_VER(svr) == SVR_8569) { 435 if(IS_SVR_REV(svr, 1, 0)) 436 do_fixup_by_compat_u32(blob, "fsl,qe", 437 "fsl,qe-num-snums", 46, 1); 438 else 439 do_fixup_by_compat_u32(blob, "fsl,qe", 440 "fsl,qe-num-snums", 76, 1); 441 } 442 } 443 #endif 444 445 /** 446 * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree 447 * 448 * The binding for an Fman firmware node is documented in 449 * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains 450 * the actual Fman firmware binary data. The operating system is expected to 451 * be able to parse the binary data to determine any attributes it needs. 452 */ 453 #ifdef CONFIG_SYS_DPAA_FMAN 454 void fdt_fixup_fman_firmware(void *blob) 455 { 456 int rc, fmnode, fwnode = -1; 457 uint32_t phandle; 458 struct qe_firmware *fmanfw; 459 const struct qe_header *hdr; 460 unsigned int length; 461 uint32_t crc; 462 const char *p; 463 464 /* The first Fman we find will contain the actual firmware. */ 465 fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); 466 if (fmnode < 0) 467 /* Exit silently if there are no Fman devices */ 468 return; 469 470 /* If we already have a firmware node, then also exit silently. */ 471 if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) 472 return; 473 474 /* If the environment variable is not set, then exit silently */ 475 p = getenv("fman_ucode"); 476 if (!p) 477 return; 478 479 fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0); 480 if (!fmanfw) 481 return; 482 483 hdr = &fmanfw->header; 484 length = be32_to_cpu(hdr->length); 485 486 /* Verify the firmware. */ 487 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || 488 (hdr->magic[2] != 'F')) { 489 printf("Data at %p is not an Fman firmware\n", fmanfw); 490 return; 491 } 492 493 if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { 494 printf("Fman firmware at %p is too large (size=%u)\n", 495 fmanfw, length); 496 return; 497 } 498 499 length -= sizeof(u32); /* Subtract the size of the CRC */ 500 crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); 501 if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { 502 printf("Fman firmware at %p has invalid CRC\n", fmanfw); 503 return; 504 } 505 506 /* Increase the size of the fdt to make room for the node. */ 507 rc = fdt_increase_size(blob, fmanfw->header.length); 508 if (rc < 0) { 509 printf("Unable to make room for Fman firmware: %s\n", 510 fdt_strerror(rc)); 511 return; 512 } 513 514 /* Create the firmware node. */ 515 fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); 516 if (fwnode < 0) { 517 char s[64]; 518 fdt_get_path(blob, fmnode, s, sizeof(s)); 519 printf("Could not add firmware node to %s: %s\n", s, 520 fdt_strerror(fwnode)); 521 return; 522 } 523 rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); 524 if (rc < 0) { 525 char s[64]; 526 fdt_get_path(blob, fwnode, s, sizeof(s)); 527 printf("Could not add compatible property to node %s: %s\n", s, 528 fdt_strerror(rc)); 529 return; 530 } 531 phandle = fdt_create_phandle(blob, fwnode); 532 if (!phandle) { 533 char s[64]; 534 fdt_get_path(blob, fwnode, s, sizeof(s)); 535 printf("Could not add phandle property to node %s: %s\n", s, 536 fdt_strerror(rc)); 537 return; 538 } 539 rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); 540 if (rc < 0) { 541 char s[64]; 542 fdt_get_path(blob, fwnode, s, sizeof(s)); 543 printf("Could not add firmware property to node %s: %s\n", s, 544 fdt_strerror(rc)); 545 return; 546 } 547 548 /* Find all other Fman nodes and point them to the firmware node. */ 549 while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { 550 rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); 551 if (rc < 0) { 552 char s[64]; 553 fdt_get_path(blob, fmnode, s, sizeof(s)); 554 printf("Could not add pointer property to node %s: %s\n", 555 s, fdt_strerror(rc)); 556 return; 557 } 558 } 559 } 560 #else 561 #define fdt_fixup_fman_firmware(x) 562 #endif 563 564 #if defined(CONFIG_PPC_P4080) 565 static void fdt_fixup_usb(void *fdt) 566 { 567 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 568 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 569 int off; 570 571 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph"); 572 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) != 573 FSL_CORENET_RCWSR11_EC1_FM1_USB1) 574 fdt_status_disabled(fdt, off); 575 576 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr"); 577 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) != 578 FSL_CORENET_RCWSR11_EC2_USB2) 579 fdt_status_disabled(fdt, off); 580 } 581 #else 582 #define fdt_fixup_usb(x) 583 #endif 584 585 void ft_cpu_setup(void *blob, bd_t *bd) 586 { 587 int off; 588 int val; 589 sys_info_t sysinfo; 590 591 /* delete crypto node if not on an E-processor */ 592 if (!IS_E_PROCESSOR(get_svr())) 593 fdt_fixup_crypto_node(blob, 0); 594 595 fdt_fixup_ethernet(blob); 596 597 fdt_add_enet_stashing(blob); 598 599 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 600 "timebase-frequency", get_tbclk(), 1); 601 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 602 "bus-frequency", bd->bi_busfreq, 1); 603 get_sys_info(&sysinfo); 604 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 605 while (off != -FDT_ERR_NOTFOUND) { 606 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 607 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); 608 fdt_setprop(blob, off, "clock-frequency", &val, 4); 609 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 610 "cpu", 4); 611 } 612 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 613 "bus-frequency", bd->bi_busfreq, 1); 614 615 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", 616 "bus-frequency", gd->lbc_clk, 1); 617 do_fixup_by_compat_u32(blob, "fsl,elbc", 618 "bus-frequency", gd->lbc_clk, 1); 619 #ifdef CONFIG_QE 620 ft_qe_setup(blob); 621 ft_fixup_qe_snum(blob); 622 #endif 623 624 fdt_fixup_fman_firmware(blob); 625 626 #ifdef CONFIG_SYS_NS16550 627 do_fixup_by_compat_u32(blob, "ns16550", 628 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 629 #endif 630 631 #ifdef CONFIG_CPM2 632 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 633 "current-speed", bd->bi_baudrate, 1); 634 635 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 636 "clock-frequency", bd->bi_brgfreq, 1); 637 #endif 638 639 #ifdef CONFIG_FSL_CORENET 640 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 641 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 642 #endif 643 644 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 645 646 #ifdef CONFIG_MP 647 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 648 ft_fixup_num_cores(blob); 649 #endif 650 651 ft_fixup_cache(blob); 652 653 #if defined(CONFIG_FSL_ESDHC) 654 fdt_fixup_esdhc(blob, bd); 655 #endif 656 657 ft_fixup_dpaa_clks(blob); 658 659 #if defined(CONFIG_SYS_BMAN_MEM_PHYS) 660 fdt_portal(blob, "fsl,bman-portal", "bman-portals", 661 (u64)CONFIG_SYS_BMAN_MEM_PHYS, 662 CONFIG_SYS_BMAN_MEM_SIZE); 663 fdt_fixup_bportals(blob); 664 #endif 665 666 #if defined(CONFIG_SYS_QMAN_MEM_PHYS) 667 fdt_portal(blob, "fsl,qman-portal", "qman-portals", 668 (u64)CONFIG_SYS_QMAN_MEM_PHYS, 669 CONFIG_SYS_QMAN_MEM_SIZE); 670 671 fdt_fixup_qportals(blob); 672 #endif 673 674 #ifdef CONFIG_SYS_SRIO 675 ft_srio_setup(blob); 676 #endif 677 678 /* 679 * system-clock = CCB clock/2 680 * Here gd->bus_clk = CCB clock 681 * We are using the system clock as 1588 Timer reference 682 * clock source select 683 */ 684 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", 685 "timer-frequency", gd->bus_clk/2, 1); 686 687 /* 688 * clock-freq should change to clock-frequency and 689 * flexcan-v1.0 should change to p1010-flexcan respectively 690 * in the future. 691 */ 692 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 693 "clock_freq", gd->bus_clk/2, 1); 694 695 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 696 "clock-frequency", gd->bus_clk/2, 1); 697 698 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan", 699 "clock-frequency", gd->bus_clk/2, 1); 700 701 fdt_fixup_usb(blob); 702 } 703 704 /* 705 * For some CCSR devices, we only have the virtual address, not the physical 706 * address. This is because we map CCSR as a whole, so we typically don't need 707 * a macro for the physical address of any device within CCSR. In this case, 708 * we calculate the physical address of that device using it's the difference 709 * between the virtual address of the device and the virtual address of the 710 * beginning of CCSR. 711 */ 712 #define CCSR_VIRT_TO_PHYS(x) \ 713 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) 714 715 static void msg(const char *name, uint64_t uaddr, uint64_t daddr) 716 { 717 printf("Warning: U-Boot configured %s at address %llx,\n" 718 "but the device tree has it at %llx\n", name, uaddr, daddr); 719 } 720 721 /* 722 * Verify the device tree 723 * 724 * This function compares several CONFIG_xxx macros that contain physical 725 * addresses with the corresponding nodes in the device tree, to see if 726 * the physical addresses are all correct. For example, if 727 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address 728 * of the first UART. We convert this to a physical address and compare 729 * that with the physical address of the first ns16550-compatible node 730 * in the device tree. If they don't match, then we display a warning. 731 * 732 * Returns 1 on success, 0 on failure 733 */ 734 int ft_verify_fdt(void *fdt) 735 { 736 uint64_t addr = 0; 737 int aliases; 738 int off; 739 740 /* First check the CCSR base address */ 741 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); 742 if (off > 0) 743 addr = fdt_get_base_address(fdt, off); 744 745 if (!addr) { 746 printf("Warning: could not determine base CCSR address in " 747 "device tree\n"); 748 /* No point in checking anything else */ 749 return 0; 750 } 751 752 if (addr != CONFIG_SYS_CCSRBAR_PHYS) { 753 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); 754 /* No point in checking anything else */ 755 return 0; 756 } 757 758 /* 759 * Check some nodes via aliases. We assume that U-Boot and the device 760 * tree enumerate the devices equally. E.g. the first serial port in 761 * U-Boot is the same as "serial0" in the device tree. 762 */ 763 aliases = fdt_path_offset(fdt, "/aliases"); 764 if (aliases > 0) { 765 #ifdef CONFIG_SYS_NS16550_COM1 766 if (!fdt_verify_alias_address(fdt, aliases, "serial0", 767 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) 768 return 0; 769 #endif 770 771 #ifdef CONFIG_SYS_NS16550_COM2 772 if (!fdt_verify_alias_address(fdt, aliases, "serial1", 773 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) 774 return 0; 775 #endif 776 } 777 778 /* 779 * The localbus node is typically a root node, even though the lbc 780 * controller is part of CCSR. If we were to put the lbc node under 781 * the SOC node, then the 'ranges' property in the lbc node would 782 * translate through the 'ranges' property of the parent SOC node, and 783 * we don't want that. Since it's a separate node, it's possible for 784 * the 'reg' property to be wrong, so check it here. For now, we 785 * only check for "fsl,elbc" nodes. 786 */ 787 #ifdef CONFIG_SYS_LBC_ADDR 788 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); 789 if (off > 0) { 790 const u32 *reg = fdt_getprop(fdt, off, "reg", NULL); 791 if (reg) { 792 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); 793 794 addr = fdt_translate_address(fdt, off, reg); 795 if (uaddr != addr) { 796 msg("the localbus", uaddr, addr); 797 return 0; 798 } 799 } 800 } 801 #endif 802 803 return 1; 804 } 805