1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <libfdt.h> 28 #include <fdt_support.h> 29 #include <asm/processor.h> 30 #include <linux/ctype.h> 31 #include <asm/io.h> 32 #include <asm/fsl_portals.h> 33 #ifdef CONFIG_FSL_ESDHC 34 #include <fsl_esdhc.h> 35 #endif 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 extern void ft_qe_setup(void *blob); 40 extern void ft_fixup_num_cores(void *blob); 41 extern void ft_srio_setup(void *blob); 42 43 #ifdef CONFIG_MP 44 #include "mp.h" 45 46 void ft_fixup_cpu(void *blob, u64 memory_limit) 47 { 48 int off; 49 ulong spin_tbl_addr = get_spin_phys_addr(); 50 u32 bootpg = determine_mp_bootpg(); 51 u32 id = get_my_id(); 52 const char *enable_method; 53 54 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 55 while (off != -FDT_ERR_NOTFOUND) { 56 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 57 58 if (reg) { 59 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; 60 val = cpu_to_fdt32(val); 61 if (*reg == id) { 62 fdt_setprop_string(blob, off, "status", 63 "okay"); 64 } else { 65 fdt_setprop_string(blob, off, "status", 66 "disabled"); 67 } 68 69 if (hold_cores_in_reset(0)) { 70 #ifdef CONFIG_FSL_CORENET 71 /* Cores held in reset, use BRR to release */ 72 enable_method = "fsl,brr-holdoff"; 73 #else 74 /* Cores held in reset, use EEBPCR to release */ 75 enable_method = "fsl,eebpcr-holdoff"; 76 #endif 77 } else { 78 /* Cores out of reset and in a spin-loop */ 79 enable_method = "spin-table"; 80 81 fdt_setprop(blob, off, "cpu-release-addr", 82 &val, sizeof(val)); 83 } 84 85 fdt_setprop_string(blob, off, "enable-method", 86 enable_method); 87 } else { 88 printf ("cpu NULL\n"); 89 } 90 off = fdt_node_offset_by_prop_value(blob, off, 91 "device_type", "cpu", 4); 92 } 93 94 /* Reserve the boot page so OSes dont use it */ 95 if ((u64)bootpg < memory_limit) { 96 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 97 if (off < 0) 98 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); 99 } 100 } 101 #endif 102 103 #ifdef CONFIG_SYS_FSL_CPC 104 static inline void ft_fixup_l3cache(void *blob, int off) 105 { 106 u32 line_size, num_ways, size, num_sets; 107 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 108 u32 cfg0 = in_be32(&cpc->cpccfg0); 109 110 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 111 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 112 line_size = CPC_CFG0_LINE_SZ(cfg0); 113 num_sets = size / (line_size * num_ways); 114 115 fdt_setprop(blob, off, "cache-unified", NULL, 0); 116 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 117 fdt_setprop_cell(blob, off, "cache-size", size); 118 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 119 fdt_setprop_cell(blob, off, "cache-level", 3); 120 #ifdef CONFIG_SYS_CACHE_STASHING 121 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 122 #endif 123 } 124 #else 125 #define ft_fixup_l3cache(x, y) 126 #endif 127 128 #if defined(CONFIG_L2_CACHE) 129 /* return size in kilobytes */ 130 static inline u32 l2cache_size(void) 131 { 132 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 133 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 134 u32 ver = SVR_SOC_VER(get_svr()); 135 136 switch (l2siz_field) { 137 case 0x0: 138 break; 139 case 0x1: 140 if (ver == SVR_8540 || ver == SVR_8560 || 141 ver == SVR_8541 || ver == SVR_8541_E || 142 ver == SVR_8555 || ver == SVR_8555_E) 143 return 128; 144 else 145 return 256; 146 break; 147 case 0x2: 148 if (ver == SVR_8540 || ver == SVR_8560 || 149 ver == SVR_8541 || ver == SVR_8541_E || 150 ver == SVR_8555 || ver == SVR_8555_E) 151 return 256; 152 else 153 return 512; 154 break; 155 case 0x3: 156 return 1024; 157 break; 158 } 159 160 return 0; 161 } 162 163 static inline void ft_fixup_l2cache(void *blob) 164 { 165 int len, off; 166 u32 *ph; 167 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 168 char compat_buf[38]; 169 170 const u32 line_size = 32; 171 const u32 num_ways = 8; 172 const u32 size = l2cache_size() * 1024; 173 const u32 num_sets = size / (line_size * num_ways); 174 175 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 176 if (off < 0) { 177 debug("no cpu node fount\n"); 178 return; 179 } 180 181 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 182 183 if (ph == NULL) { 184 debug("no next-level-cache property\n"); 185 return ; 186 } 187 188 off = fdt_node_offset_by_phandle(blob, *ph); 189 if (off < 0) { 190 printf("%s: %s\n", __func__, fdt_strerror(off)); 191 return ; 192 } 193 194 if (cpu) { 195 if (isdigit(cpu->name[0])) 196 len = sprintf(compat_buf, 197 "fsl,mpc%s-l2-cache-controller", cpu->name); 198 else 199 len = sprintf(compat_buf, 200 "fsl,%c%s-l2-cache-controller", 201 tolower(cpu->name[0]), cpu->name + 1); 202 203 sprintf(&compat_buf[len + 1], "cache"); 204 } 205 fdt_setprop(blob, off, "cache-unified", NULL, 0); 206 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 207 fdt_setprop_cell(blob, off, "cache-size", size); 208 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 209 fdt_setprop_cell(blob, off, "cache-level", 2); 210 fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf)); 211 212 /* we dont bother w/L3 since no platform of this type has one */ 213 } 214 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 215 static inline void ft_fixup_l2cache(void *blob) 216 { 217 int off, l2_off, l3_off = -1; 218 u32 *ph; 219 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 220 u32 size, line_size, num_ways, num_sets; 221 222 size = (l2cfg0 & 0x3fff) * 64 * 1024; 223 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 224 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 225 num_sets = size / (line_size * num_ways); 226 227 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 228 229 while (off != -FDT_ERR_NOTFOUND) { 230 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 231 232 if (ph == NULL) { 233 debug("no next-level-cache property\n"); 234 goto next; 235 } 236 237 l2_off = fdt_node_offset_by_phandle(blob, *ph); 238 if (l2_off < 0) { 239 printf("%s: %s\n", __func__, fdt_strerror(off)); 240 goto next; 241 } 242 243 #ifdef CONFIG_SYS_CACHE_STASHING 244 { 245 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 246 if (reg) 247 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 248 (*reg * 2) + 32 + 1); 249 } 250 #endif 251 252 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 253 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); 254 fdt_setprop_cell(blob, l2_off, "cache-size", size); 255 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 256 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 257 fdt_setprop(blob, l2_off, "compatible", "cache", 6); 258 259 if (l3_off < 0) { 260 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 261 262 if (ph == NULL) { 263 debug("no next-level-cache property\n"); 264 goto next; 265 } 266 l3_off = *ph; 267 } 268 next: 269 off = fdt_node_offset_by_prop_value(blob, off, 270 "device_type", "cpu", 4); 271 } 272 if (l3_off > 0) { 273 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 274 if (l3_off < 0) { 275 printf("%s: %s\n", __func__, fdt_strerror(off)); 276 return ; 277 } 278 ft_fixup_l3cache(blob, l3_off); 279 } 280 } 281 #else 282 #define ft_fixup_l2cache(x) 283 #endif 284 285 static inline void ft_fixup_cache(void *blob) 286 { 287 int off; 288 289 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 290 291 while (off != -FDT_ERR_NOTFOUND) { 292 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 293 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 294 u32 isize, iline_size, inum_sets, inum_ways; 295 u32 dsize, dline_size, dnum_sets, dnum_ways; 296 297 /* d-side config */ 298 dsize = (l1cfg0 & 0x7ff) * 1024; 299 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 300 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 301 dnum_sets = dsize / (dline_size * dnum_ways); 302 303 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 304 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 305 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 306 307 #ifdef CONFIG_SYS_CACHE_STASHING 308 { 309 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 310 if (reg) 311 fdt_setprop_cell(blob, off, "cache-stash-id", 312 (*reg * 2) + 32 + 0); 313 } 314 #endif 315 316 /* i-side config */ 317 isize = (l1cfg1 & 0x7ff) * 1024; 318 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 319 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 320 inum_sets = isize / (iline_size * inum_ways); 321 322 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 323 fdt_setprop_cell(blob, off, "i-cache-size", isize); 324 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 325 326 off = fdt_node_offset_by_prop_value(blob, off, 327 "device_type", "cpu", 4); 328 } 329 330 ft_fixup_l2cache(blob); 331 } 332 333 334 void fdt_add_enet_stashing(void *fdt) 335 { 336 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 337 338 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 339 340 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 341 } 342 343 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 344 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 345 unsigned long freq) 346 { 347 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 348 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 349 350 if (off >= 0) { 351 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 352 if (off > 0) 353 printf("WARNING enable to set clock-frequency " 354 "for %s: %s\n", compat, fdt_strerror(off)); 355 } 356 } 357 358 static void ft_fixup_dpaa_clks(void *blob) 359 { 360 sys_info_t sysinfo; 361 362 get_sys_info(&sysinfo); 363 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 364 sysinfo.freqFMan[0]); 365 366 #if (CONFIG_SYS_NUM_FMAN == 2) 367 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 368 sysinfo.freqFMan[1]); 369 #endif 370 371 #ifdef CONFIG_SYS_DPAA_PME 372 do_fixup_by_compat_u32(blob, "fsl,pme", 373 "clock-frequency", sysinfo.freqPME, 1); 374 #endif 375 } 376 #else 377 #define ft_fixup_dpaa_clks(x) 378 #endif 379 380 #ifdef CONFIG_QE 381 static void ft_fixup_qe_snum(void *blob) 382 { 383 unsigned int svr; 384 385 svr = mfspr(SPRN_SVR); 386 if (SVR_SOC_VER(svr) == SVR_8569_E) { 387 if(IS_SVR_REV(svr, 1, 0)) 388 do_fixup_by_compat_u32(blob, "fsl,qe", 389 "fsl,qe-num-snums", 46, 1); 390 else 391 do_fixup_by_compat_u32(blob, "fsl,qe", 392 "fsl,qe-num-snums", 76, 1); 393 } 394 } 395 #endif 396 397 void ft_cpu_setup(void *blob, bd_t *bd) 398 { 399 int off; 400 int val; 401 sys_info_t sysinfo; 402 403 /* delete crypto node if not on an E-processor */ 404 if (!IS_E_PROCESSOR(get_svr())) 405 fdt_fixup_crypto_node(blob, 0); 406 407 fdt_fixup_ethernet(blob); 408 409 fdt_add_enet_stashing(blob); 410 411 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 412 "timebase-frequency", get_tbclk(), 1); 413 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 414 "bus-frequency", bd->bi_busfreq, 1); 415 get_sys_info(&sysinfo); 416 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 417 while (off != -FDT_ERR_NOTFOUND) { 418 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 419 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); 420 fdt_setprop(blob, off, "clock-frequency", &val, 4); 421 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 422 "cpu", 4); 423 } 424 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 425 "bus-frequency", bd->bi_busfreq, 1); 426 427 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", 428 "bus-frequency", gd->lbc_clk, 1); 429 do_fixup_by_compat_u32(blob, "fsl,elbc", 430 "bus-frequency", gd->lbc_clk, 1); 431 #ifdef CONFIG_QE 432 ft_qe_setup(blob); 433 ft_fixup_qe_snum(blob); 434 #endif 435 436 #ifdef CONFIG_SYS_NS16550 437 do_fixup_by_compat_u32(blob, "ns16550", 438 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 439 #endif 440 441 #ifdef CONFIG_CPM2 442 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 443 "current-speed", bd->bi_baudrate, 1); 444 445 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 446 "clock-frequency", bd->bi_brgfreq, 1); 447 #endif 448 449 #ifdef CONFIG_FSL_CORENET 450 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 451 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 452 #endif 453 454 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 455 456 #ifdef CONFIG_MP 457 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 458 ft_fixup_num_cores(blob); 459 #endif 460 461 ft_fixup_cache(blob); 462 463 #if defined(CONFIG_FSL_ESDHC) 464 fdt_fixup_esdhc(blob, bd); 465 #endif 466 467 ft_fixup_dpaa_clks(blob); 468 469 #if defined(CONFIG_SYS_BMAN_MEM_PHYS) 470 fdt_portal(blob, "fsl,bman-portal", "bman-portals", 471 (u64)CONFIG_SYS_BMAN_MEM_PHYS, 472 CONFIG_SYS_BMAN_MEM_SIZE); 473 #endif 474 475 #if defined(CONFIG_SYS_QMAN_MEM_PHYS) 476 fdt_portal(blob, "fsl,qman-portal", "qman-portals", 477 (u64)CONFIG_SYS_QMAN_MEM_PHYS, 478 CONFIG_SYS_QMAN_MEM_SIZE); 479 480 fdt_fixup_qportals(blob); 481 #endif 482 483 #ifdef CONFIG_SYS_SRIO 484 ft_srio_setup(blob); 485 #endif 486 } 487