1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <libfdt.h> 12 #include <fdt_support.h> 13 #include <asm/processor.h> 14 #include <linux/ctype.h> 15 #include <asm/io.h> 16 #include <asm/fsl_portals.h> 17 #include <hwconfig.h> 18 #ifdef CONFIG_FSL_ESDHC 19 #include <fsl_esdhc.h> 20 #endif 21 #include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 extern void ft_qe_setup(void *blob); 26 extern void ft_fixup_num_cores(void *blob); 27 extern void ft_srio_setup(void *blob); 28 29 #ifdef CONFIG_MP 30 #include "mp.h" 31 32 void ft_fixup_cpu(void *blob, u64 memory_limit) 33 { 34 int off; 35 phys_addr_t spin_tbl_addr = get_spin_phys_addr(); 36 u32 bootpg = determine_mp_bootpg(NULL); 37 u32 id = get_my_id(); 38 const char *enable_method; 39 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 40 int ret; 41 int tdm_hwconfig_enabled = 0; 42 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 43 #endif 44 45 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 46 while (off != -FDT_ERR_NOTFOUND) { 47 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 48 49 if (reg) { 50 u32 phys_cpu_id = thread_to_core(*reg); 51 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr; 52 val = cpu_to_fdt64(val); 53 if (*reg == id) { 54 fdt_setprop_string(blob, off, "status", 55 "okay"); 56 } else { 57 fdt_setprop_string(blob, off, "status", 58 "disabled"); 59 } 60 61 if (hold_cores_in_reset(0)) { 62 #ifdef CONFIG_FSL_CORENET 63 /* Cores held in reset, use BRR to release */ 64 enable_method = "fsl,brr-holdoff"; 65 #else 66 /* Cores held in reset, use EEBPCR to release */ 67 enable_method = "fsl,eebpcr-holdoff"; 68 #endif 69 } else { 70 /* Cores out of reset and in a spin-loop */ 71 enable_method = "spin-table"; 72 73 fdt_setprop(blob, off, "cpu-release-addr", 74 &val, sizeof(val)); 75 } 76 77 fdt_setprop_string(blob, off, "enable-method", 78 enable_method); 79 } else { 80 printf ("cpu NULL\n"); 81 } 82 off = fdt_node_offset_by_prop_value(blob, off, 83 "device_type", "cpu", 4); 84 } 85 86 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 87 #define CONFIG_MEM_HOLE_16M 0x1000000 88 /* 89 * Extract hwconfig from environment. 90 * Search for tdm entry in hwconfig. 91 */ 92 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 93 if (ret > 0) 94 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 95 96 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */ 97 if (tdm_hwconfig_enabled) { 98 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE, 99 CONFIG_MEM_HOLE_16M); 100 if (off < 0) 101 printf("Failed to reserve memory for tdm: %s\n", 102 fdt_strerror(off)); 103 } 104 #endif 105 106 /* Reserve the boot page so OSes dont use it */ 107 if ((u64)bootpg < memory_limit) { 108 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 109 if (off < 0) 110 printf("Failed to reserve memory for bootpg: %s\n", 111 fdt_strerror(off)); 112 } 113 114 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR 115 /* 116 * Reserve the default boot page so OSes dont use it. 117 * The default boot page is always mapped to bootpg above using 118 * boot page translation. 119 */ 120 if (0xfffff000ull < memory_limit) { 121 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096); 122 if (off < 0) { 123 printf("Failed to reserve memory for 0xfffff000: %s\n", 124 fdt_strerror(off)); 125 } 126 } 127 #endif 128 129 /* Reserve spin table page */ 130 if (spin_tbl_addr < memory_limit) { 131 off = fdt_add_mem_rsv(blob, 132 (spin_tbl_addr & ~0xffful), 4096); 133 if (off < 0) 134 printf("Failed to reserve memory for spin table: %s\n", 135 fdt_strerror(off)); 136 } 137 } 138 #endif 139 140 #ifdef CONFIG_SYS_FSL_CPC 141 static inline void ft_fixup_l3cache(void *blob, int off) 142 { 143 u32 line_size, num_ways, size, num_sets; 144 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 145 u32 cfg0 = in_be32(&cpc->cpccfg0); 146 147 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 148 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 149 line_size = CPC_CFG0_LINE_SZ(cfg0); 150 num_sets = size / (line_size * num_ways); 151 152 fdt_setprop(blob, off, "cache-unified", NULL, 0); 153 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 154 fdt_setprop_cell(blob, off, "cache-size", size); 155 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 156 fdt_setprop_cell(blob, off, "cache-level", 3); 157 #ifdef CONFIG_SYS_CACHE_STASHING 158 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 159 #endif 160 } 161 #else 162 #define ft_fixup_l3cache(x, y) 163 #endif 164 165 #if defined(CONFIG_L2_CACHE) 166 /* return size in kilobytes */ 167 static inline u32 l2cache_size(void) 168 { 169 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 170 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 171 u32 ver = SVR_SOC_VER(get_svr()); 172 173 switch (l2siz_field) { 174 case 0x0: 175 break; 176 case 0x1: 177 if (ver == SVR_8540 || ver == SVR_8560 || 178 ver == SVR_8541 || ver == SVR_8555) 179 return 128; 180 else 181 return 256; 182 break; 183 case 0x2: 184 if (ver == SVR_8540 || ver == SVR_8560 || 185 ver == SVR_8541 || ver == SVR_8555) 186 return 256; 187 else 188 return 512; 189 break; 190 case 0x3: 191 return 1024; 192 break; 193 } 194 195 return 0; 196 } 197 198 static inline void ft_fixup_l2cache(void *blob) 199 { 200 int len, off; 201 u32 *ph; 202 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 203 204 const u32 line_size = 32; 205 const u32 num_ways = 8; 206 const u32 size = l2cache_size() * 1024; 207 const u32 num_sets = size / (line_size * num_ways); 208 209 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 210 if (off < 0) { 211 debug("no cpu node fount\n"); 212 return; 213 } 214 215 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 216 217 if (ph == NULL) { 218 debug("no next-level-cache property\n"); 219 return ; 220 } 221 222 off = fdt_node_offset_by_phandle(blob, *ph); 223 if (off < 0) { 224 printf("%s: %s\n", __func__, fdt_strerror(off)); 225 return ; 226 } 227 228 if (cpu) { 229 char buf[40]; 230 231 if (isdigit(cpu->name[0])) { 232 /* MPCxxxx, where xxxx == 4-digit number */ 233 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", 234 cpu->name) + 1; 235 } else { 236 /* Pxxxx or Txxxx, where xxxx == 4-digit number */ 237 len = sprintf(buf, "fsl,%c%s-l2-cache-controller", 238 tolower(cpu->name[0]), cpu->name + 1) + 1; 239 } 240 241 /* 242 * append "cache" after the NULL character that the previous 243 * sprintf wrote. This is how a device tree stores multiple 244 * strings in a property. 245 */ 246 len += sprintf(buf + len, "cache") + 1; 247 248 fdt_setprop(blob, off, "compatible", buf, len); 249 } 250 fdt_setprop(blob, off, "cache-unified", NULL, 0); 251 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 252 fdt_setprop_cell(blob, off, "cache-size", size); 253 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 254 fdt_setprop_cell(blob, off, "cache-level", 2); 255 256 /* we dont bother w/L3 since no platform of this type has one */ 257 } 258 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \ 259 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 260 static inline void ft_fixup_l2cache(void *blob) 261 { 262 int off, l2_off, l3_off = -1; 263 u32 *ph; 264 #ifdef CONFIG_BACKSIDE_L2_CACHE 265 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 266 #else 267 struct ccsr_cluster_l2 *l2cache = 268 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); 269 u32 l2cfg0 = in_be32(&l2cache->l2cfg0); 270 #endif 271 u32 size, line_size, num_ways, num_sets; 272 int has_l2 = 1; 273 274 /* P2040/P2040E has no L2, so dont set any L2 props */ 275 if (SVR_SOC_VER(get_svr()) == SVR_P2040) 276 has_l2 = 0; 277 278 size = (l2cfg0 & 0x3fff) * 64 * 1024; 279 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 280 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 281 num_sets = size / (line_size * num_ways); 282 283 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 284 285 while (off != -FDT_ERR_NOTFOUND) { 286 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 287 288 if (ph == NULL) { 289 debug("no next-level-cache property\n"); 290 goto next; 291 } 292 293 l2_off = fdt_node_offset_by_phandle(blob, *ph); 294 if (l2_off < 0) { 295 printf("%s: %s\n", __func__, fdt_strerror(off)); 296 goto next; 297 } 298 299 if (has_l2) { 300 #ifdef CONFIG_SYS_CACHE_STASHING 301 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 302 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 303 /* Only initialize every eighth thread */ 304 if (reg && !((*reg) % 8)) { 305 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 306 (*reg / 4) + 32 + 1); 307 } 308 #else 309 if (reg) { 310 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 311 (*reg * 2) + 32 + 1); 312 } 313 #endif 314 #endif 315 316 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 317 fdt_setprop_cell(blob, l2_off, "cache-block-size", 318 line_size); 319 fdt_setprop_cell(blob, l2_off, "cache-size", size); 320 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 321 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 322 fdt_setprop(blob, l2_off, "compatible", "cache", 6); 323 } 324 325 if (l3_off < 0) { 326 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 327 328 if (ph == NULL) { 329 debug("no next-level-cache property\n"); 330 goto next; 331 } 332 l3_off = *ph; 333 } 334 next: 335 off = fdt_node_offset_by_prop_value(blob, off, 336 "device_type", "cpu", 4); 337 } 338 if (l3_off > 0) { 339 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 340 if (l3_off < 0) { 341 printf("%s: %s\n", __func__, fdt_strerror(off)); 342 return ; 343 } 344 ft_fixup_l3cache(blob, l3_off); 345 } 346 } 347 #else 348 #define ft_fixup_l2cache(x) 349 #endif 350 351 static inline void ft_fixup_cache(void *blob) 352 { 353 int off; 354 355 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 356 357 while (off != -FDT_ERR_NOTFOUND) { 358 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 359 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 360 u32 isize, iline_size, inum_sets, inum_ways; 361 u32 dsize, dline_size, dnum_sets, dnum_ways; 362 363 /* d-side config */ 364 dsize = (l1cfg0 & 0x7ff) * 1024; 365 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 366 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 367 dnum_sets = dsize / (dline_size * dnum_ways); 368 369 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 370 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 371 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 372 373 #ifdef CONFIG_SYS_CACHE_STASHING 374 { 375 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 376 if (reg) 377 fdt_setprop_cell(blob, off, "cache-stash-id", 378 (*reg * 2) + 32 + 0); 379 } 380 #endif 381 382 /* i-side config */ 383 isize = (l1cfg1 & 0x7ff) * 1024; 384 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 385 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 386 inum_sets = isize / (iline_size * inum_ways); 387 388 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 389 fdt_setprop_cell(blob, off, "i-cache-size", isize); 390 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 391 392 off = fdt_node_offset_by_prop_value(blob, off, 393 "device_type", "cpu", 4); 394 } 395 396 ft_fixup_l2cache(blob); 397 } 398 399 400 void fdt_add_enet_stashing(void *fdt) 401 { 402 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 403 404 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 405 406 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 407 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); 408 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); 409 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); 410 } 411 412 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 413 #ifdef CONFIG_SYS_DPAA_FMAN 414 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 415 unsigned long freq) 416 { 417 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 418 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 419 420 if (off >= 0) { 421 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 422 if (off > 0) 423 printf("WARNING enable to set clock-frequency " 424 "for %s: %s\n", compat, fdt_strerror(off)); 425 } 426 } 427 #endif 428 429 static void ft_fixup_dpaa_clks(void *blob) 430 { 431 sys_info_t sysinfo; 432 433 get_sys_info(&sysinfo); 434 #ifdef CONFIG_SYS_DPAA_FMAN 435 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 436 sysinfo.freq_fman[0]); 437 438 #if (CONFIG_SYS_NUM_FMAN == 2) 439 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 440 sysinfo.freq_fman[1]); 441 #endif 442 #endif 443 444 #ifdef CONFIG_SYS_DPAA_QBMAN 445 do_fixup_by_compat_u32(blob, "fsl,qman", 446 "clock-frequency", sysinfo.freq_qman, 1); 447 #endif 448 449 #ifdef CONFIG_SYS_DPAA_PME 450 do_fixup_by_compat_u32(blob, "fsl,pme", 451 "clock-frequency", sysinfo.freq_pme, 1); 452 #endif 453 } 454 #else 455 #define ft_fixup_dpaa_clks(x) 456 #endif 457 458 #ifdef CONFIG_QE 459 static void ft_fixup_qe_snum(void *blob) 460 { 461 unsigned int svr; 462 463 svr = mfspr(SPRN_SVR); 464 if (SVR_SOC_VER(svr) == SVR_8569) { 465 if(IS_SVR_REV(svr, 1, 0)) 466 do_fixup_by_compat_u32(blob, "fsl,qe", 467 "fsl,qe-num-snums", 46, 1); 468 else 469 do_fixup_by_compat_u32(blob, "fsl,qe", 470 "fsl,qe-num-snums", 76, 1); 471 } 472 } 473 #endif 474 475 /** 476 * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree 477 * 478 * The binding for an Fman firmware node is documented in 479 * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains 480 * the actual Fman firmware binary data. The operating system is expected to 481 * be able to parse the binary data to determine any attributes it needs. 482 */ 483 #ifdef CONFIG_SYS_DPAA_FMAN 484 void fdt_fixup_fman_firmware(void *blob) 485 { 486 int rc, fmnode, fwnode = -1; 487 uint32_t phandle; 488 struct qe_firmware *fmanfw; 489 const struct qe_header *hdr; 490 unsigned int length; 491 uint32_t crc; 492 const char *p; 493 494 /* The first Fman we find will contain the actual firmware. */ 495 fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); 496 if (fmnode < 0) 497 /* Exit silently if there are no Fman devices */ 498 return; 499 500 /* If we already have a firmware node, then also exit silently. */ 501 if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) 502 return; 503 504 /* If the environment variable is not set, then exit silently */ 505 p = getenv("fman_ucode"); 506 if (!p) 507 return; 508 509 fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16); 510 if (!fmanfw) 511 return; 512 513 hdr = &fmanfw->header; 514 length = be32_to_cpu(hdr->length); 515 516 /* Verify the firmware. */ 517 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || 518 (hdr->magic[2] != 'F')) { 519 printf("Data at %p is not an Fman firmware\n", fmanfw); 520 return; 521 } 522 523 if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { 524 printf("Fman firmware at %p is too large (size=%u)\n", 525 fmanfw, length); 526 return; 527 } 528 529 length -= sizeof(u32); /* Subtract the size of the CRC */ 530 crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); 531 if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { 532 printf("Fman firmware at %p has invalid CRC\n", fmanfw); 533 return; 534 } 535 536 /* Increase the size of the fdt to make room for the node. */ 537 rc = fdt_increase_size(blob, fmanfw->header.length); 538 if (rc < 0) { 539 printf("Unable to make room for Fman firmware: %s\n", 540 fdt_strerror(rc)); 541 return; 542 } 543 544 /* Create the firmware node. */ 545 fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); 546 if (fwnode < 0) { 547 char s[64]; 548 fdt_get_path(blob, fmnode, s, sizeof(s)); 549 printf("Could not add firmware node to %s: %s\n", s, 550 fdt_strerror(fwnode)); 551 return; 552 } 553 rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); 554 if (rc < 0) { 555 char s[64]; 556 fdt_get_path(blob, fwnode, s, sizeof(s)); 557 printf("Could not add compatible property to node %s: %s\n", s, 558 fdt_strerror(rc)); 559 return; 560 } 561 phandle = fdt_create_phandle(blob, fwnode); 562 if (!phandle) { 563 char s[64]; 564 fdt_get_path(blob, fwnode, s, sizeof(s)); 565 printf("Could not add phandle property to node %s: %s\n", s, 566 fdt_strerror(rc)); 567 return; 568 } 569 rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); 570 if (rc < 0) { 571 char s[64]; 572 fdt_get_path(blob, fwnode, s, sizeof(s)); 573 printf("Could not add firmware property to node %s: %s\n", s, 574 fdt_strerror(rc)); 575 return; 576 } 577 578 /* Find all other Fman nodes and point them to the firmware node. */ 579 while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { 580 rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); 581 if (rc < 0) { 582 char s[64]; 583 fdt_get_path(blob, fmnode, s, sizeof(s)); 584 printf("Could not add pointer property to node %s: %s\n", 585 s, fdt_strerror(rc)); 586 return; 587 } 588 } 589 } 590 #else 591 #define fdt_fixup_fman_firmware(x) 592 #endif 593 594 #if defined(CONFIG_PPC_P4080) 595 static void fdt_fixup_usb(void *fdt) 596 { 597 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 598 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 599 int off; 600 601 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph"); 602 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) != 603 FSL_CORENET_RCWSR11_EC1_FM1_USB1) 604 fdt_status_disabled(fdt, off); 605 606 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr"); 607 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) != 608 FSL_CORENET_RCWSR11_EC2_USB2) 609 fdt_status_disabled(fdt, off); 610 } 611 #else 612 #define fdt_fixup_usb(x) 613 #endif 614 615 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \ 616 defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) 617 void fdt_fixup_dma3(void *blob) 618 { 619 /* the 3rd DMA is not functional if SRIO2 is chosen */ 620 int nodeoff; 621 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 622 623 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) 624 #if defined(CONFIG_PPC_T2080) 625 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 626 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 627 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 628 629 switch (srds_prtcl_s2) { 630 case 0x29: 631 case 0x2d: 632 case 0x2e: 633 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 634 defined(CONFIG_PPC_T4080) 635 u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & 636 FSL_CORENET2_RCWSR4_SRDS4_PRTCL; 637 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; 638 639 switch (srds_prtcl_s4) { 640 case 6: 641 case 8: 642 case 14: 643 case 16: 644 #endif 645 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma", 646 CONFIG_SYS_ELO3_DMA3); 647 if (nodeoff > 0) 648 fdt_status_disabled(blob, nodeoff); 649 else 650 printf("WARNING: unable to disable dma3\n"); 651 break; 652 default: 653 break; 654 } 655 } 656 #else 657 #define fdt_fixup_dma3(x) 658 #endif 659 660 #if defined(CONFIG_PPC_T1040) 661 static void fdt_fixup_l2_switch(void *blob) 662 { 663 uchar l2swaddr[6]; 664 int node; 665 666 /* The l2switch node from device-tree has 667 * compatible string "vitesse-9953" */ 668 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953"); 669 if (node == -FDT_ERR_NOTFOUND) 670 /* no l2switch node has been found */ 671 return; 672 673 /* Get MAC address for the l2switch from "l2switchaddr"*/ 674 if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) { 675 printf("Warning: MAC address for l2switch not found\n"); 676 memset(l2swaddr, 0, sizeof(l2swaddr)); 677 } 678 679 /* Add MAC address to l2switch node */ 680 fdt_setprop(blob, node, "local-mac-address", l2swaddr, 681 sizeof(l2swaddr)); 682 } 683 #else 684 #define fdt_fixup_l2_switch(x) 685 #endif 686 687 void ft_cpu_setup(void *blob, bd_t *bd) 688 { 689 int off; 690 int val; 691 int len; 692 sys_info_t sysinfo; 693 694 /* delete crypto node if not on an E-processor */ 695 if (!IS_E_PROCESSOR(get_svr())) 696 fdt_fixup_crypto_node(blob, 0); 697 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 698 else { 699 ccsr_sec_t __iomem *sec; 700 701 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 702 fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms)); 703 } 704 #endif 705 706 fdt_fixup_ethernet(blob); 707 708 fdt_add_enet_stashing(blob); 709 710 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV 711 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1 712 #endif 713 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 714 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV, 715 1); 716 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 717 "bus-frequency", bd->bi_busfreq, 1); 718 get_sys_info(&sysinfo); 719 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 720 while (off != -FDT_ERR_NOTFOUND) { 721 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); 722 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]); 723 fdt_setprop(blob, off, "clock-frequency", &val, 4); 724 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 725 "cpu", 4); 726 } 727 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 728 "bus-frequency", bd->bi_busfreq, 1); 729 730 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", 731 "bus-frequency", gd->arch.lbc_clk, 1); 732 do_fixup_by_compat_u32(blob, "fsl,elbc", 733 "bus-frequency", gd->arch.lbc_clk, 1); 734 #ifdef CONFIG_QE 735 ft_qe_setup(blob); 736 ft_fixup_qe_snum(blob); 737 #endif 738 739 fdt_fixup_fman_firmware(blob); 740 741 #ifdef CONFIG_SYS_NS16550 742 do_fixup_by_compat_u32(blob, "ns16550", 743 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 744 #endif 745 746 #ifdef CONFIG_CPM2 747 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 748 "current-speed", gd->baudrate, 1); 749 750 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 751 "clock-frequency", bd->bi_brgfreq, 1); 752 #endif 753 754 #ifdef CONFIG_FSL_CORENET 755 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 756 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 757 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0", 758 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 759 do_fixup_by_compat_u32(blob, "fsl,mpic", 760 "clock-frequency", get_bus_freq(0)/2, 1); 761 #else 762 do_fixup_by_compat_u32(blob, "fsl,mpic", 763 "clock-frequency", get_bus_freq(0), 1); 764 #endif 765 766 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 767 768 #ifdef CONFIG_MP 769 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 770 ft_fixup_num_cores(blob); 771 #endif 772 773 ft_fixup_cache(blob); 774 775 #if defined(CONFIG_FSL_ESDHC) 776 fdt_fixup_esdhc(blob, bd); 777 #endif 778 779 ft_fixup_dpaa_clks(blob); 780 781 #if defined(CONFIG_SYS_BMAN_MEM_PHYS) 782 fdt_portal(blob, "fsl,bman-portal", "bman-portals", 783 (u64)CONFIG_SYS_BMAN_MEM_PHYS, 784 CONFIG_SYS_BMAN_MEM_SIZE); 785 fdt_fixup_bportals(blob); 786 #endif 787 788 #if defined(CONFIG_SYS_QMAN_MEM_PHYS) 789 fdt_portal(blob, "fsl,qman-portal", "qman-portals", 790 (u64)CONFIG_SYS_QMAN_MEM_PHYS, 791 CONFIG_SYS_QMAN_MEM_SIZE); 792 793 fdt_fixup_qportals(blob); 794 #endif 795 796 #ifdef CONFIG_SYS_SRIO 797 ft_srio_setup(blob); 798 #endif 799 800 /* 801 * system-clock = CCB clock/2 802 * Here gd->bus_clk = CCB clock 803 * We are using the system clock as 1588 Timer reference 804 * clock source select 805 */ 806 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", 807 "timer-frequency", gd->bus_clk/2, 1); 808 809 /* 810 * clock-freq should change to clock-frequency and 811 * flexcan-v1.0 should change to p1010-flexcan respectively 812 * in the future. 813 */ 814 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 815 "clock_freq", gd->bus_clk/2, 1); 816 817 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 818 "clock-frequency", gd->bus_clk/2, 1); 819 820 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan", 821 "clock-frequency", gd->bus_clk/2, 1); 822 823 fdt_fixup_usb(blob); 824 825 fdt_fixup_l2_switch(blob); 826 827 fdt_fixup_dma3(blob); 828 } 829 830 /* 831 * For some CCSR devices, we only have the virtual address, not the physical 832 * address. This is because we map CCSR as a whole, so we typically don't need 833 * a macro for the physical address of any device within CCSR. In this case, 834 * we calculate the physical address of that device using it's the difference 835 * between the virtual address of the device and the virtual address of the 836 * beginning of CCSR. 837 */ 838 #define CCSR_VIRT_TO_PHYS(x) \ 839 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) 840 841 static void msg(const char *name, uint64_t uaddr, uint64_t daddr) 842 { 843 printf("Warning: U-Boot configured %s at address %llx,\n" 844 "but the device tree has it at %llx\n", name, uaddr, daddr); 845 } 846 847 /* 848 * Verify the device tree 849 * 850 * This function compares several CONFIG_xxx macros that contain physical 851 * addresses with the corresponding nodes in the device tree, to see if 852 * the physical addresses are all correct. For example, if 853 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address 854 * of the first UART. We convert this to a physical address and compare 855 * that with the physical address of the first ns16550-compatible node 856 * in the device tree. If they don't match, then we display a warning. 857 * 858 * Returns 1 on success, 0 on failure 859 */ 860 int ft_verify_fdt(void *fdt) 861 { 862 uint64_t addr = 0; 863 int aliases; 864 int off; 865 866 /* First check the CCSR base address */ 867 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); 868 if (off > 0) 869 addr = fdt_get_base_address(fdt, off); 870 871 if (!addr) { 872 printf("Warning: could not determine base CCSR address in " 873 "device tree\n"); 874 /* No point in checking anything else */ 875 return 0; 876 } 877 878 if (addr != CONFIG_SYS_CCSRBAR_PHYS) { 879 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); 880 /* No point in checking anything else */ 881 return 0; 882 } 883 884 /* 885 * Check some nodes via aliases. We assume that U-Boot and the device 886 * tree enumerate the devices equally. E.g. the first serial port in 887 * U-Boot is the same as "serial0" in the device tree. 888 */ 889 aliases = fdt_path_offset(fdt, "/aliases"); 890 if (aliases > 0) { 891 #ifdef CONFIG_SYS_NS16550_COM1 892 if (!fdt_verify_alias_address(fdt, aliases, "serial0", 893 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) 894 return 0; 895 #endif 896 897 #ifdef CONFIG_SYS_NS16550_COM2 898 if (!fdt_verify_alias_address(fdt, aliases, "serial1", 899 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) 900 return 0; 901 #endif 902 } 903 904 /* 905 * The localbus node is typically a root node, even though the lbc 906 * controller is part of CCSR. If we were to put the lbc node under 907 * the SOC node, then the 'ranges' property in the lbc node would 908 * translate through the 'ranges' property of the parent SOC node, and 909 * we don't want that. Since it's a separate node, it's possible for 910 * the 'reg' property to be wrong, so check it here. For now, we 911 * only check for "fsl,elbc" nodes. 912 */ 913 #ifdef CONFIG_SYS_LBC_ADDR 914 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); 915 if (off > 0) { 916 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL); 917 if (reg) { 918 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); 919 920 addr = fdt_translate_address(fdt, off, reg); 921 if (uaddr != addr) { 922 msg("the localbus", uaddr, addr); 923 return 0; 924 } 925 } 926 } 927 #endif 928 929 return 1; 930 } 931