1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <libfdt.h> 12 #include <fdt_support.h> 13 #include <asm/processor.h> 14 #include <linux/ctype.h> 15 #include <asm/io.h> 16 #include <asm/fsl_portals.h> 17 #ifdef CONFIG_FSL_ESDHC 18 #include <fsl_esdhc.h> 19 #endif 20 #include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 extern void ft_qe_setup(void *blob); 25 extern void ft_fixup_num_cores(void *blob); 26 extern void ft_srio_setup(void *blob); 27 28 #ifdef CONFIG_MP 29 #include "mp.h" 30 31 void ft_fixup_cpu(void *blob, u64 memory_limit) 32 { 33 int off; 34 phys_addr_t spin_tbl_addr = get_spin_phys_addr(); 35 u32 bootpg = determine_mp_bootpg(NULL); 36 u32 id = get_my_id(); 37 const char *enable_method; 38 39 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 40 while (off != -FDT_ERR_NOTFOUND) { 41 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 42 43 if (reg) { 44 u32 phys_cpu_id = thread_to_core(*reg); 45 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr; 46 val = cpu_to_fdt64(val); 47 if (*reg == id) { 48 fdt_setprop_string(blob, off, "status", 49 "okay"); 50 } else { 51 fdt_setprop_string(blob, off, "status", 52 "disabled"); 53 } 54 55 if (hold_cores_in_reset(0)) { 56 #ifdef CONFIG_FSL_CORENET 57 /* Cores held in reset, use BRR to release */ 58 enable_method = "fsl,brr-holdoff"; 59 #else 60 /* Cores held in reset, use EEBPCR to release */ 61 enable_method = "fsl,eebpcr-holdoff"; 62 #endif 63 } else { 64 /* Cores out of reset and in a spin-loop */ 65 enable_method = "spin-table"; 66 67 fdt_setprop(blob, off, "cpu-release-addr", 68 &val, sizeof(val)); 69 } 70 71 fdt_setprop_string(blob, off, "enable-method", 72 enable_method); 73 } else { 74 printf ("cpu NULL\n"); 75 } 76 off = fdt_node_offset_by_prop_value(blob, off, 77 "device_type", "cpu", 4); 78 } 79 80 /* Reserve the boot page so OSes dont use it */ 81 if ((u64)bootpg < memory_limit) { 82 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 83 if (off < 0) 84 printf("Failed to reserve memory for bootpg: %s\n", 85 fdt_strerror(off)); 86 } 87 88 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR 89 /* 90 * Reserve the default boot page so OSes dont use it. 91 * The default boot page is always mapped to bootpg above using 92 * boot page translation. 93 */ 94 if (0xfffff000ull < memory_limit) { 95 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096); 96 if (off < 0) { 97 printf("Failed to reserve memory for 0xfffff000: %s\n", 98 fdt_strerror(off)); 99 } 100 } 101 #endif 102 103 /* Reserve spin table page */ 104 if (spin_tbl_addr < memory_limit) { 105 off = fdt_add_mem_rsv(blob, 106 (spin_tbl_addr & ~0xffful), 4096); 107 if (off < 0) 108 printf("Failed to reserve memory for spin table: %s\n", 109 fdt_strerror(off)); 110 } 111 } 112 #endif 113 114 #ifdef CONFIG_SYS_FSL_CPC 115 static inline void ft_fixup_l3cache(void *blob, int off) 116 { 117 u32 line_size, num_ways, size, num_sets; 118 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 119 u32 cfg0 = in_be32(&cpc->cpccfg0); 120 121 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 122 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 123 line_size = CPC_CFG0_LINE_SZ(cfg0); 124 num_sets = size / (line_size * num_ways); 125 126 fdt_setprop(blob, off, "cache-unified", NULL, 0); 127 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 128 fdt_setprop_cell(blob, off, "cache-size", size); 129 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 130 fdt_setprop_cell(blob, off, "cache-level", 3); 131 #ifdef CONFIG_SYS_CACHE_STASHING 132 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 133 #endif 134 } 135 #else 136 #define ft_fixup_l3cache(x, y) 137 #endif 138 139 #if defined(CONFIG_L2_CACHE) 140 /* return size in kilobytes */ 141 static inline u32 l2cache_size(void) 142 { 143 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 144 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 145 u32 ver = SVR_SOC_VER(get_svr()); 146 147 switch (l2siz_field) { 148 case 0x0: 149 break; 150 case 0x1: 151 if (ver == SVR_8540 || ver == SVR_8560 || 152 ver == SVR_8541 || ver == SVR_8555) 153 return 128; 154 else 155 return 256; 156 break; 157 case 0x2: 158 if (ver == SVR_8540 || ver == SVR_8560 || 159 ver == SVR_8541 || ver == SVR_8555) 160 return 256; 161 else 162 return 512; 163 break; 164 case 0x3: 165 return 1024; 166 break; 167 } 168 169 return 0; 170 } 171 172 static inline void ft_fixup_l2cache(void *blob) 173 { 174 int len, off; 175 u32 *ph; 176 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 177 178 const u32 line_size = 32; 179 const u32 num_ways = 8; 180 const u32 size = l2cache_size() * 1024; 181 const u32 num_sets = size / (line_size * num_ways); 182 183 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 184 if (off < 0) { 185 debug("no cpu node fount\n"); 186 return; 187 } 188 189 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 190 191 if (ph == NULL) { 192 debug("no next-level-cache property\n"); 193 return ; 194 } 195 196 off = fdt_node_offset_by_phandle(blob, *ph); 197 if (off < 0) { 198 printf("%s: %s\n", __func__, fdt_strerror(off)); 199 return ; 200 } 201 202 if (cpu) { 203 char buf[40]; 204 205 if (isdigit(cpu->name[0])) { 206 /* MPCxxxx, where xxxx == 4-digit number */ 207 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", 208 cpu->name) + 1; 209 } else { 210 /* Pxxxx or Txxxx, where xxxx == 4-digit number */ 211 len = sprintf(buf, "fsl,%c%s-l2-cache-controller", 212 tolower(cpu->name[0]), cpu->name + 1) + 1; 213 } 214 215 /* 216 * append "cache" after the NULL character that the previous 217 * sprintf wrote. This is how a device tree stores multiple 218 * strings in a property. 219 */ 220 len += sprintf(buf + len, "cache") + 1; 221 222 fdt_setprop(blob, off, "compatible", buf, len); 223 } 224 fdt_setprop(blob, off, "cache-unified", NULL, 0); 225 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 226 fdt_setprop_cell(blob, off, "cache-size", size); 227 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 228 fdt_setprop_cell(blob, off, "cache-level", 2); 229 230 /* we dont bother w/L3 since no platform of this type has one */ 231 } 232 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \ 233 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 234 static inline void ft_fixup_l2cache(void *blob) 235 { 236 int off, l2_off, l3_off = -1; 237 u32 *ph; 238 #ifdef CONFIG_BACKSIDE_L2_CACHE 239 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 240 #else 241 struct ccsr_cluster_l2 *l2cache = 242 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); 243 u32 l2cfg0 = in_be32(&l2cache->l2cfg0); 244 #endif 245 u32 size, line_size, num_ways, num_sets; 246 int has_l2 = 1; 247 248 /* P2040/P2040E has no L2, so dont set any L2 props */ 249 if (SVR_SOC_VER(get_svr()) == SVR_P2040) 250 has_l2 = 0; 251 252 size = (l2cfg0 & 0x3fff) * 64 * 1024; 253 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 254 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 255 num_sets = size / (line_size * num_ways); 256 257 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 258 259 while (off != -FDT_ERR_NOTFOUND) { 260 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 261 262 if (ph == NULL) { 263 debug("no next-level-cache property\n"); 264 goto next; 265 } 266 267 l2_off = fdt_node_offset_by_phandle(blob, *ph); 268 if (l2_off < 0) { 269 printf("%s: %s\n", __func__, fdt_strerror(off)); 270 goto next; 271 } 272 273 if (has_l2) { 274 #ifdef CONFIG_SYS_CACHE_STASHING 275 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 276 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 277 /* Only initialize every eighth thread */ 278 if (reg && !((*reg) % 8)) { 279 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 280 (*reg / 4) + 32 + 1); 281 } 282 #else 283 if (reg) { 284 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 285 (*reg * 2) + 32 + 1); 286 } 287 #endif 288 #endif 289 290 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 291 fdt_setprop_cell(blob, l2_off, "cache-block-size", 292 line_size); 293 fdt_setprop_cell(blob, l2_off, "cache-size", size); 294 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 295 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 296 fdt_setprop(blob, l2_off, "compatible", "cache", 6); 297 } 298 299 if (l3_off < 0) { 300 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 301 302 if (ph == NULL) { 303 debug("no next-level-cache property\n"); 304 goto next; 305 } 306 l3_off = *ph; 307 } 308 next: 309 off = fdt_node_offset_by_prop_value(blob, off, 310 "device_type", "cpu", 4); 311 } 312 if (l3_off > 0) { 313 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 314 if (l3_off < 0) { 315 printf("%s: %s\n", __func__, fdt_strerror(off)); 316 return ; 317 } 318 ft_fixup_l3cache(blob, l3_off); 319 } 320 } 321 #else 322 #define ft_fixup_l2cache(x) 323 #endif 324 325 static inline void ft_fixup_cache(void *blob) 326 { 327 int off; 328 329 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 330 331 while (off != -FDT_ERR_NOTFOUND) { 332 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 333 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 334 u32 isize, iline_size, inum_sets, inum_ways; 335 u32 dsize, dline_size, dnum_sets, dnum_ways; 336 337 /* d-side config */ 338 dsize = (l1cfg0 & 0x7ff) * 1024; 339 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 340 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 341 dnum_sets = dsize / (dline_size * dnum_ways); 342 343 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 344 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 345 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 346 347 #ifdef CONFIG_SYS_CACHE_STASHING 348 { 349 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 350 if (reg) 351 fdt_setprop_cell(blob, off, "cache-stash-id", 352 (*reg * 2) + 32 + 0); 353 } 354 #endif 355 356 /* i-side config */ 357 isize = (l1cfg1 & 0x7ff) * 1024; 358 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 359 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 360 inum_sets = isize / (iline_size * inum_ways); 361 362 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 363 fdt_setprop_cell(blob, off, "i-cache-size", isize); 364 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 365 366 off = fdt_node_offset_by_prop_value(blob, off, 367 "device_type", "cpu", 4); 368 } 369 370 ft_fixup_l2cache(blob); 371 } 372 373 374 void fdt_add_enet_stashing(void *fdt) 375 { 376 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 377 378 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 379 380 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 381 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); 382 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); 383 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); 384 } 385 386 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 387 #ifdef CONFIG_SYS_DPAA_FMAN 388 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 389 unsigned long freq) 390 { 391 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 392 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 393 394 if (off >= 0) { 395 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 396 if (off > 0) 397 printf("WARNING enable to set clock-frequency " 398 "for %s: %s\n", compat, fdt_strerror(off)); 399 } 400 } 401 #endif 402 403 static void ft_fixup_dpaa_clks(void *blob) 404 { 405 sys_info_t sysinfo; 406 407 get_sys_info(&sysinfo); 408 #ifdef CONFIG_SYS_DPAA_FMAN 409 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 410 sysinfo.freq_fman[0]); 411 412 #if (CONFIG_SYS_NUM_FMAN == 2) 413 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 414 sysinfo.freq_fman[1]); 415 #endif 416 #endif 417 418 #ifdef CONFIG_SYS_DPAA_QBMAN 419 do_fixup_by_compat_u32(blob, "fsl,qman", 420 "clock-frequency", sysinfo.freq_qman, 1); 421 #endif 422 423 #ifdef CONFIG_SYS_DPAA_PME 424 do_fixup_by_compat_u32(blob, "fsl,pme", 425 "clock-frequency", sysinfo.freq_pme, 1); 426 #endif 427 } 428 #else 429 #define ft_fixup_dpaa_clks(x) 430 #endif 431 432 #ifdef CONFIG_QE 433 static void ft_fixup_qe_snum(void *blob) 434 { 435 unsigned int svr; 436 437 svr = mfspr(SPRN_SVR); 438 if (SVR_SOC_VER(svr) == SVR_8569) { 439 if(IS_SVR_REV(svr, 1, 0)) 440 do_fixup_by_compat_u32(blob, "fsl,qe", 441 "fsl,qe-num-snums", 46, 1); 442 else 443 do_fixup_by_compat_u32(blob, "fsl,qe", 444 "fsl,qe-num-snums", 76, 1); 445 } 446 } 447 #endif 448 449 /** 450 * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree 451 * 452 * The binding for an Fman firmware node is documented in 453 * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains 454 * the actual Fman firmware binary data. The operating system is expected to 455 * be able to parse the binary data to determine any attributes it needs. 456 */ 457 #ifdef CONFIG_SYS_DPAA_FMAN 458 void fdt_fixup_fman_firmware(void *blob) 459 { 460 int rc, fmnode, fwnode = -1; 461 uint32_t phandle; 462 struct qe_firmware *fmanfw; 463 const struct qe_header *hdr; 464 unsigned int length; 465 uint32_t crc; 466 const char *p; 467 468 /* The first Fman we find will contain the actual firmware. */ 469 fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); 470 if (fmnode < 0) 471 /* Exit silently if there are no Fman devices */ 472 return; 473 474 /* If we already have a firmware node, then also exit silently. */ 475 if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) 476 return; 477 478 /* If the environment variable is not set, then exit silently */ 479 p = getenv("fman_ucode"); 480 if (!p) 481 return; 482 483 fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16); 484 if (!fmanfw) 485 return; 486 487 hdr = &fmanfw->header; 488 length = be32_to_cpu(hdr->length); 489 490 /* Verify the firmware. */ 491 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || 492 (hdr->magic[2] != 'F')) { 493 printf("Data at %p is not an Fman firmware\n", fmanfw); 494 return; 495 } 496 497 if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { 498 printf("Fman firmware at %p is too large (size=%u)\n", 499 fmanfw, length); 500 return; 501 } 502 503 length -= sizeof(u32); /* Subtract the size of the CRC */ 504 crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); 505 if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { 506 printf("Fman firmware at %p has invalid CRC\n", fmanfw); 507 return; 508 } 509 510 /* Increase the size of the fdt to make room for the node. */ 511 rc = fdt_increase_size(blob, fmanfw->header.length); 512 if (rc < 0) { 513 printf("Unable to make room for Fman firmware: %s\n", 514 fdt_strerror(rc)); 515 return; 516 } 517 518 /* Create the firmware node. */ 519 fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); 520 if (fwnode < 0) { 521 char s[64]; 522 fdt_get_path(blob, fmnode, s, sizeof(s)); 523 printf("Could not add firmware node to %s: %s\n", s, 524 fdt_strerror(fwnode)); 525 return; 526 } 527 rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); 528 if (rc < 0) { 529 char s[64]; 530 fdt_get_path(blob, fwnode, s, sizeof(s)); 531 printf("Could not add compatible property to node %s: %s\n", s, 532 fdt_strerror(rc)); 533 return; 534 } 535 phandle = fdt_create_phandle(blob, fwnode); 536 if (!phandle) { 537 char s[64]; 538 fdt_get_path(blob, fwnode, s, sizeof(s)); 539 printf("Could not add phandle property to node %s: %s\n", s, 540 fdt_strerror(rc)); 541 return; 542 } 543 rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); 544 if (rc < 0) { 545 char s[64]; 546 fdt_get_path(blob, fwnode, s, sizeof(s)); 547 printf("Could not add firmware property to node %s: %s\n", s, 548 fdt_strerror(rc)); 549 return; 550 } 551 552 /* Find all other Fman nodes and point them to the firmware node. */ 553 while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { 554 rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); 555 if (rc < 0) { 556 char s[64]; 557 fdt_get_path(blob, fmnode, s, sizeof(s)); 558 printf("Could not add pointer property to node %s: %s\n", 559 s, fdt_strerror(rc)); 560 return; 561 } 562 } 563 } 564 #else 565 #define fdt_fixup_fman_firmware(x) 566 #endif 567 568 #if defined(CONFIG_PPC_P4080) 569 static void fdt_fixup_usb(void *fdt) 570 { 571 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 572 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 573 int off; 574 575 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph"); 576 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) != 577 FSL_CORENET_RCWSR11_EC1_FM1_USB1) 578 fdt_status_disabled(fdt, off); 579 580 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr"); 581 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) != 582 FSL_CORENET_RCWSR11_EC2_USB2) 583 fdt_status_disabled(fdt, off); 584 } 585 #else 586 #define fdt_fixup_usb(x) 587 #endif 588 589 #if defined(CONFIG_PPC_T1040) 590 static void fdt_fixup_l2_switch(void *blob) 591 { 592 uchar l2swaddr[6]; 593 int node; 594 595 /* The l2switch node from device-tree has 596 * compatible string "vitesse-9953" */ 597 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953"); 598 if (node == -FDT_ERR_NOTFOUND) 599 /* no l2switch node has been found */ 600 return; 601 602 /* Get MAC address for the l2switch from "l2switchaddr"*/ 603 if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) { 604 printf("Warning: MAC address for l2switch not found\n"); 605 memset(l2swaddr, 0, sizeof(l2swaddr)); 606 } 607 608 /* Add MAC address to l2switch node */ 609 fdt_setprop(blob, node, "local-mac-address", l2swaddr, 610 sizeof(l2swaddr)); 611 } 612 #else 613 #define fdt_fixup_l2_switch(x) 614 #endif 615 616 void ft_cpu_setup(void *blob, bd_t *bd) 617 { 618 int off; 619 int val; 620 int len; 621 sys_info_t sysinfo; 622 623 /* delete crypto node if not on an E-processor */ 624 if (!IS_E_PROCESSOR(get_svr())) 625 fdt_fixup_crypto_node(blob, 0); 626 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 627 else { 628 ccsr_sec_t __iomem *sec; 629 630 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 631 fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms)); 632 } 633 #endif 634 635 fdt_fixup_ethernet(blob); 636 637 fdt_add_enet_stashing(blob); 638 639 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV 640 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1 641 #endif 642 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 643 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV, 644 1); 645 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 646 "bus-frequency", bd->bi_busfreq, 1); 647 get_sys_info(&sysinfo); 648 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 649 while (off != -FDT_ERR_NOTFOUND) { 650 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); 651 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]); 652 fdt_setprop(blob, off, "clock-frequency", &val, 4); 653 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 654 "cpu", 4); 655 } 656 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 657 "bus-frequency", bd->bi_busfreq, 1); 658 659 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", 660 "bus-frequency", gd->arch.lbc_clk, 1); 661 do_fixup_by_compat_u32(blob, "fsl,elbc", 662 "bus-frequency", gd->arch.lbc_clk, 1); 663 #ifdef CONFIG_QE 664 ft_qe_setup(blob); 665 ft_fixup_qe_snum(blob); 666 #endif 667 668 fdt_fixup_fman_firmware(blob); 669 670 #ifdef CONFIG_SYS_NS16550 671 do_fixup_by_compat_u32(blob, "ns16550", 672 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 673 #endif 674 675 #ifdef CONFIG_CPM2 676 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 677 "current-speed", bd->bi_baudrate, 1); 678 679 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 680 "clock-frequency", bd->bi_brgfreq, 1); 681 #endif 682 683 #ifdef CONFIG_FSL_CORENET 684 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 685 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 686 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0", 687 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 688 do_fixup_by_compat_u32(blob, "fsl,mpic", 689 "clock-frequency", get_bus_freq(0)/2, 1); 690 #else 691 do_fixup_by_compat_u32(blob, "fsl,mpic", 692 "clock-frequency", get_bus_freq(0), 1); 693 #endif 694 695 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 696 697 #ifdef CONFIG_MP 698 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 699 ft_fixup_num_cores(blob); 700 #endif 701 702 ft_fixup_cache(blob); 703 704 #if defined(CONFIG_FSL_ESDHC) 705 fdt_fixup_esdhc(blob, bd); 706 #endif 707 708 ft_fixup_dpaa_clks(blob); 709 710 #if defined(CONFIG_SYS_BMAN_MEM_PHYS) 711 fdt_portal(blob, "fsl,bman-portal", "bman-portals", 712 (u64)CONFIG_SYS_BMAN_MEM_PHYS, 713 CONFIG_SYS_BMAN_MEM_SIZE); 714 fdt_fixup_bportals(blob); 715 #endif 716 717 #if defined(CONFIG_SYS_QMAN_MEM_PHYS) 718 fdt_portal(blob, "fsl,qman-portal", "qman-portals", 719 (u64)CONFIG_SYS_QMAN_MEM_PHYS, 720 CONFIG_SYS_QMAN_MEM_SIZE); 721 722 fdt_fixup_qportals(blob); 723 #endif 724 725 #ifdef CONFIG_SYS_SRIO 726 ft_srio_setup(blob); 727 #endif 728 729 /* 730 * system-clock = CCB clock/2 731 * Here gd->bus_clk = CCB clock 732 * We are using the system clock as 1588 Timer reference 733 * clock source select 734 */ 735 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", 736 "timer-frequency", gd->bus_clk/2, 1); 737 738 /* 739 * clock-freq should change to clock-frequency and 740 * flexcan-v1.0 should change to p1010-flexcan respectively 741 * in the future. 742 */ 743 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 744 "clock_freq", gd->bus_clk/2, 1); 745 746 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 747 "clock-frequency", gd->bus_clk/2, 1); 748 749 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan", 750 "clock-frequency", gd->bus_clk/2, 1); 751 752 fdt_fixup_usb(blob); 753 754 fdt_fixup_l2_switch(blob); 755 } 756 757 /* 758 * For some CCSR devices, we only have the virtual address, not the physical 759 * address. This is because we map CCSR as a whole, so we typically don't need 760 * a macro for the physical address of any device within CCSR. In this case, 761 * we calculate the physical address of that device using it's the difference 762 * between the virtual address of the device and the virtual address of the 763 * beginning of CCSR. 764 */ 765 #define CCSR_VIRT_TO_PHYS(x) \ 766 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) 767 768 static void msg(const char *name, uint64_t uaddr, uint64_t daddr) 769 { 770 printf("Warning: U-Boot configured %s at address %llx,\n" 771 "but the device tree has it at %llx\n", name, uaddr, daddr); 772 } 773 774 /* 775 * Verify the device tree 776 * 777 * This function compares several CONFIG_xxx macros that contain physical 778 * addresses with the corresponding nodes in the device tree, to see if 779 * the physical addresses are all correct. For example, if 780 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address 781 * of the first UART. We convert this to a physical address and compare 782 * that with the physical address of the first ns16550-compatible node 783 * in the device tree. If they don't match, then we display a warning. 784 * 785 * Returns 1 on success, 0 on failure 786 */ 787 int ft_verify_fdt(void *fdt) 788 { 789 uint64_t addr = 0; 790 int aliases; 791 int off; 792 793 /* First check the CCSR base address */ 794 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); 795 if (off > 0) 796 addr = fdt_get_base_address(fdt, off); 797 798 if (!addr) { 799 printf("Warning: could not determine base CCSR address in " 800 "device tree\n"); 801 /* No point in checking anything else */ 802 return 0; 803 } 804 805 if (addr != CONFIG_SYS_CCSRBAR_PHYS) { 806 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); 807 /* No point in checking anything else */ 808 return 0; 809 } 810 811 /* 812 * Check some nodes via aliases. We assume that U-Boot and the device 813 * tree enumerate the devices equally. E.g. the first serial port in 814 * U-Boot is the same as "serial0" in the device tree. 815 */ 816 aliases = fdt_path_offset(fdt, "/aliases"); 817 if (aliases > 0) { 818 #ifdef CONFIG_SYS_NS16550_COM1 819 if (!fdt_verify_alias_address(fdt, aliases, "serial0", 820 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) 821 return 0; 822 #endif 823 824 #ifdef CONFIG_SYS_NS16550_COM2 825 if (!fdt_verify_alias_address(fdt, aliases, "serial1", 826 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) 827 return 0; 828 #endif 829 } 830 831 /* 832 * The localbus node is typically a root node, even though the lbc 833 * controller is part of CCSR. If we were to put the lbc node under 834 * the SOC node, then the 'ranges' property in the lbc node would 835 * translate through the 'ranges' property of the parent SOC node, and 836 * we don't want that. Since it's a separate node, it's possible for 837 * the 'reg' property to be wrong, so check it here. For now, we 838 * only check for "fsl,elbc" nodes. 839 */ 840 #ifdef CONFIG_SYS_LBC_ADDR 841 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); 842 if (off > 0) { 843 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL); 844 if (reg) { 845 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); 846 847 addr = fdt_translate_address(fdt, off, reg); 848 if (uaddr != addr) { 849 msg("the localbus", uaddr, addr); 850 return 0; 851 } 852 } 853 } 854 #endif 855 856 return 1; 857 } 858