1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <libfdt.h> 28 #include <fdt_support.h> 29 #include <asm/processor.h> 30 #include <linux/ctype.h> 31 #include <asm/io.h> 32 #include <asm/fsl_portals.h> 33 #ifdef CONFIG_FSL_ESDHC 34 #include <fsl_esdhc.h> 35 #endif 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 extern void ft_qe_setup(void *blob); 40 extern void ft_fixup_num_cores(void *blob); 41 extern void ft_srio_setup(void *blob); 42 43 #ifdef CONFIG_MP 44 #include "mp.h" 45 46 void ft_fixup_cpu(void *blob, u64 memory_limit) 47 { 48 int off; 49 ulong spin_tbl_addr = get_spin_phys_addr(); 50 u32 bootpg = determine_mp_bootpg(); 51 u32 id = get_my_id(); 52 const char *enable_method; 53 54 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 55 while (off != -FDT_ERR_NOTFOUND) { 56 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 57 58 if (reg) { 59 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; 60 val = cpu_to_fdt32(val); 61 if (*reg == id) { 62 fdt_setprop_string(blob, off, "status", 63 "okay"); 64 } else { 65 fdt_setprop_string(blob, off, "status", 66 "disabled"); 67 } 68 69 if (hold_cores_in_reset(0)) { 70 #ifdef CONFIG_FSL_CORENET 71 /* Cores held in reset, use BRR to release */ 72 enable_method = "fsl,brr-holdoff"; 73 #else 74 /* Cores held in reset, use EEBPCR to release */ 75 enable_method = "fsl,eebpcr-holdoff"; 76 #endif 77 } else { 78 /* Cores out of reset and in a spin-loop */ 79 enable_method = "spin-table"; 80 81 fdt_setprop(blob, off, "cpu-release-addr", 82 &val, sizeof(val)); 83 } 84 85 fdt_setprop_string(blob, off, "enable-method", 86 enable_method); 87 } else { 88 printf ("cpu NULL\n"); 89 } 90 off = fdt_node_offset_by_prop_value(blob, off, 91 "device_type", "cpu", 4); 92 } 93 94 /* Reserve the boot page so OSes dont use it */ 95 if ((u64)bootpg < memory_limit) { 96 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 97 if (off < 0) 98 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); 99 } 100 } 101 #endif 102 103 #ifdef CONFIG_SYS_FSL_CPC 104 static inline void ft_fixup_l3cache(void *blob, int off) 105 { 106 u32 line_size, num_ways, size, num_sets; 107 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 108 u32 cfg0 = in_be32(&cpc->cpccfg0); 109 110 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 111 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 112 line_size = CPC_CFG0_LINE_SZ(cfg0); 113 num_sets = size / (line_size * num_ways); 114 115 fdt_setprop(blob, off, "cache-unified", NULL, 0); 116 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 117 fdt_setprop_cell(blob, off, "cache-size", size); 118 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 119 fdt_setprop_cell(blob, off, "cache-level", 3); 120 #ifdef CONFIG_SYS_CACHE_STASHING 121 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 122 #endif 123 } 124 #else 125 #define ft_fixup_l3cache(x, y) 126 #endif 127 128 #if defined(CONFIG_L2_CACHE) 129 /* return size in kilobytes */ 130 static inline u32 l2cache_size(void) 131 { 132 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 133 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 134 u32 ver = SVR_SOC_VER(get_svr()); 135 136 switch (l2siz_field) { 137 case 0x0: 138 break; 139 case 0x1: 140 if (ver == SVR_8540 || ver == SVR_8560 || 141 ver == SVR_8541 || ver == SVR_8541_E || 142 ver == SVR_8555 || ver == SVR_8555_E) 143 return 128; 144 else 145 return 256; 146 break; 147 case 0x2: 148 if (ver == SVR_8540 || ver == SVR_8560 || 149 ver == SVR_8541 || ver == SVR_8541_E || 150 ver == SVR_8555 || ver == SVR_8555_E) 151 return 256; 152 else 153 return 512; 154 break; 155 case 0x3: 156 return 1024; 157 break; 158 } 159 160 return 0; 161 } 162 163 static inline void ft_fixup_l2cache(void *blob) 164 { 165 int len, off; 166 u32 *ph; 167 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 168 169 const u32 line_size = 32; 170 const u32 num_ways = 8; 171 const u32 size = l2cache_size() * 1024; 172 const u32 num_sets = size / (line_size * num_ways); 173 174 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 175 if (off < 0) { 176 debug("no cpu node fount\n"); 177 return; 178 } 179 180 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 181 182 if (ph == NULL) { 183 debug("no next-level-cache property\n"); 184 return ; 185 } 186 187 off = fdt_node_offset_by_phandle(blob, *ph); 188 if (off < 0) { 189 printf("%s: %s\n", __func__, fdt_strerror(off)); 190 return ; 191 } 192 193 if (cpu) { 194 char buf[40]; 195 196 if (isdigit(cpu->name[0])) { 197 /* MPCxxxx, where xxxx == 4-digit number */ 198 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", 199 cpu->name) + 1; 200 } else { 201 /* Pxxxx or Txxxx, where xxxx == 4-digit number */ 202 len = sprintf(buf, "fsl,%c%s-l2-cache-controller", 203 tolower(cpu->name[0]), cpu->name + 1) + 1; 204 } 205 206 /* 207 * append "cache" after the NULL character that the previous 208 * sprintf wrote. This is how a device tree stores multiple 209 * strings in a property. 210 */ 211 len += sprintf(buf + len, "cache") + 1; 212 213 fdt_setprop(blob, off, "compatible", buf, len); 214 } 215 fdt_setprop(blob, off, "cache-unified", NULL, 0); 216 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 217 fdt_setprop_cell(blob, off, "cache-size", size); 218 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 219 fdt_setprop_cell(blob, off, "cache-level", 2); 220 221 /* we dont bother w/L3 since no platform of this type has one */ 222 } 223 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 224 static inline void ft_fixup_l2cache(void *blob) 225 { 226 int off, l2_off, l3_off = -1; 227 u32 *ph; 228 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 229 u32 size, line_size, num_ways, num_sets; 230 231 size = (l2cfg0 & 0x3fff) * 64 * 1024; 232 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 233 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 234 num_sets = size / (line_size * num_ways); 235 236 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 237 238 while (off != -FDT_ERR_NOTFOUND) { 239 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 240 241 if (ph == NULL) { 242 debug("no next-level-cache property\n"); 243 goto next; 244 } 245 246 l2_off = fdt_node_offset_by_phandle(blob, *ph); 247 if (l2_off < 0) { 248 printf("%s: %s\n", __func__, fdt_strerror(off)); 249 goto next; 250 } 251 252 #ifdef CONFIG_SYS_CACHE_STASHING 253 { 254 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 255 if (reg) 256 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 257 (*reg * 2) + 32 + 1); 258 } 259 #endif 260 261 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 262 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); 263 fdt_setprop_cell(blob, l2_off, "cache-size", size); 264 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 265 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 266 fdt_setprop(blob, l2_off, "compatible", "cache", 6); 267 268 if (l3_off < 0) { 269 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 270 271 if (ph == NULL) { 272 debug("no next-level-cache property\n"); 273 goto next; 274 } 275 l3_off = *ph; 276 } 277 next: 278 off = fdt_node_offset_by_prop_value(blob, off, 279 "device_type", "cpu", 4); 280 } 281 if (l3_off > 0) { 282 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 283 if (l3_off < 0) { 284 printf("%s: %s\n", __func__, fdt_strerror(off)); 285 return ; 286 } 287 ft_fixup_l3cache(blob, l3_off); 288 } 289 } 290 #else 291 #define ft_fixup_l2cache(x) 292 #endif 293 294 static inline void ft_fixup_cache(void *blob) 295 { 296 int off; 297 298 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 299 300 while (off != -FDT_ERR_NOTFOUND) { 301 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 302 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 303 u32 isize, iline_size, inum_sets, inum_ways; 304 u32 dsize, dline_size, dnum_sets, dnum_ways; 305 306 /* d-side config */ 307 dsize = (l1cfg0 & 0x7ff) * 1024; 308 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 309 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 310 dnum_sets = dsize / (dline_size * dnum_ways); 311 312 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 313 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 314 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 315 316 #ifdef CONFIG_SYS_CACHE_STASHING 317 { 318 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 319 if (reg) 320 fdt_setprop_cell(blob, off, "cache-stash-id", 321 (*reg * 2) + 32 + 0); 322 } 323 #endif 324 325 /* i-side config */ 326 isize = (l1cfg1 & 0x7ff) * 1024; 327 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 328 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 329 inum_sets = isize / (iline_size * inum_ways); 330 331 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 332 fdt_setprop_cell(blob, off, "i-cache-size", isize); 333 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 334 335 off = fdt_node_offset_by_prop_value(blob, off, 336 "device_type", "cpu", 4); 337 } 338 339 ft_fixup_l2cache(blob); 340 } 341 342 343 void fdt_add_enet_stashing(void *fdt) 344 { 345 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 346 347 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 348 349 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 350 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); 351 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); 352 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); 353 } 354 355 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 356 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 357 unsigned long freq) 358 { 359 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 360 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 361 362 if (off >= 0) { 363 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 364 if (off > 0) 365 printf("WARNING enable to set clock-frequency " 366 "for %s: %s\n", compat, fdt_strerror(off)); 367 } 368 } 369 370 static void ft_fixup_dpaa_clks(void *blob) 371 { 372 sys_info_t sysinfo; 373 374 get_sys_info(&sysinfo); 375 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 376 sysinfo.freqFMan[0]); 377 378 #if (CONFIG_SYS_NUM_FMAN == 2) 379 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 380 sysinfo.freqFMan[1]); 381 #endif 382 383 #ifdef CONFIG_SYS_DPAA_PME 384 do_fixup_by_compat_u32(blob, "fsl,pme", 385 "clock-frequency", sysinfo.freqPME, 1); 386 #endif 387 } 388 #else 389 #define ft_fixup_dpaa_clks(x) 390 #endif 391 392 #ifdef CONFIG_QE 393 static void ft_fixup_qe_snum(void *blob) 394 { 395 unsigned int svr; 396 397 svr = mfspr(SPRN_SVR); 398 if (SVR_SOC_VER(svr) == SVR_8569_E) { 399 if(IS_SVR_REV(svr, 1, 0)) 400 do_fixup_by_compat_u32(blob, "fsl,qe", 401 "fsl,qe-num-snums", 46, 1); 402 else 403 do_fixup_by_compat_u32(blob, "fsl,qe", 404 "fsl,qe-num-snums", 76, 1); 405 } 406 } 407 #endif 408 409 void ft_cpu_setup(void *blob, bd_t *bd) 410 { 411 int off; 412 int val; 413 sys_info_t sysinfo; 414 415 /* delete crypto node if not on an E-processor */ 416 if (!IS_E_PROCESSOR(get_svr())) 417 fdt_fixup_crypto_node(blob, 0); 418 419 fdt_fixup_ethernet(blob); 420 421 fdt_add_enet_stashing(blob); 422 423 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 424 "timebase-frequency", get_tbclk(), 1); 425 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 426 "bus-frequency", bd->bi_busfreq, 1); 427 get_sys_info(&sysinfo); 428 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 429 while (off != -FDT_ERR_NOTFOUND) { 430 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 431 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); 432 fdt_setprop(blob, off, "clock-frequency", &val, 4); 433 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 434 "cpu", 4); 435 } 436 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 437 "bus-frequency", bd->bi_busfreq, 1); 438 439 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", 440 "bus-frequency", gd->lbc_clk, 1); 441 do_fixup_by_compat_u32(blob, "fsl,elbc", 442 "bus-frequency", gd->lbc_clk, 1); 443 #ifdef CONFIG_QE 444 ft_qe_setup(blob); 445 ft_fixup_qe_snum(blob); 446 #endif 447 448 #ifdef CONFIG_SYS_NS16550 449 do_fixup_by_compat_u32(blob, "ns16550", 450 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 451 #endif 452 453 #ifdef CONFIG_CPM2 454 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 455 "current-speed", bd->bi_baudrate, 1); 456 457 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 458 "clock-frequency", bd->bi_brgfreq, 1); 459 #endif 460 461 #ifdef CONFIG_FSL_CORENET 462 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 463 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 464 #endif 465 466 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 467 468 #ifdef CONFIG_MP 469 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 470 ft_fixup_num_cores(blob); 471 #endif 472 473 ft_fixup_cache(blob); 474 475 #if defined(CONFIG_FSL_ESDHC) 476 fdt_fixup_esdhc(blob, bd); 477 #endif 478 479 ft_fixup_dpaa_clks(blob); 480 481 #if defined(CONFIG_SYS_BMAN_MEM_PHYS) 482 fdt_portal(blob, "fsl,bman-portal", "bman-portals", 483 (u64)CONFIG_SYS_BMAN_MEM_PHYS, 484 CONFIG_SYS_BMAN_MEM_SIZE); 485 fdt_fixup_bportals(blob); 486 #endif 487 488 #if defined(CONFIG_SYS_QMAN_MEM_PHYS) 489 fdt_portal(blob, "fsl,qman-portal", "qman-portals", 490 (u64)CONFIG_SYS_QMAN_MEM_PHYS, 491 CONFIG_SYS_QMAN_MEM_SIZE); 492 493 fdt_fixup_qportals(blob); 494 #endif 495 496 #ifdef CONFIG_SYS_SRIO 497 ft_srio_setup(blob); 498 #endif 499 500 /* 501 * system-clock = CCB clock/2 502 * Here gd->bus_clk = CCB clock 503 * We are using the system clock as 1588 Timer reference 504 * clock source select 505 */ 506 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", 507 "timer-frequency", gd->bus_clk/2, 1); 508 } 509