1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <libfdt.h> 12 #include <fdt_support.h> 13 #include <asm/processor.h> 14 #include <linux/ctype.h> 15 #include <asm/io.h> 16 #include <asm/fsl_fdt.h> 17 #include <asm/fsl_portals.h> 18 #include <hwconfig.h> 19 #ifdef CONFIG_FSL_ESDHC 20 #include <fsl_esdhc.h> 21 #endif 22 #include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 extern void ft_qe_setup(void *blob); 27 extern void ft_fixup_num_cores(void *blob); 28 extern void ft_srio_setup(void *blob); 29 30 #ifdef CONFIG_MP 31 #include "mp.h" 32 33 void ft_fixup_cpu(void *blob, u64 memory_limit) 34 { 35 int off; 36 phys_addr_t spin_tbl_addr = get_spin_phys_addr(); 37 u32 bootpg = determine_mp_bootpg(NULL); 38 u32 id = get_my_id(); 39 const char *enable_method; 40 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 41 int ret; 42 int tdm_hwconfig_enabled = 0; 43 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 44 #endif 45 46 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 47 while (off != -FDT_ERR_NOTFOUND) { 48 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 49 50 if (reg) { 51 u32 phys_cpu_id = thread_to_core(*reg); 52 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr; 53 val = cpu_to_fdt64(val); 54 if (*reg == id) { 55 fdt_setprop_string(blob, off, "status", 56 "okay"); 57 } else { 58 fdt_setprop_string(blob, off, "status", 59 "disabled"); 60 } 61 62 if (hold_cores_in_reset(0)) { 63 #ifdef CONFIG_FSL_CORENET 64 /* Cores held in reset, use BRR to release */ 65 enable_method = "fsl,brr-holdoff"; 66 #else 67 /* Cores held in reset, use EEBPCR to release */ 68 enable_method = "fsl,eebpcr-holdoff"; 69 #endif 70 } else { 71 /* Cores out of reset and in a spin-loop */ 72 enable_method = "spin-table"; 73 74 fdt_setprop(blob, off, "cpu-release-addr", 75 &val, sizeof(val)); 76 } 77 78 fdt_setprop_string(blob, off, "enable-method", 79 enable_method); 80 } else { 81 printf ("cpu NULL\n"); 82 } 83 off = fdt_node_offset_by_prop_value(blob, off, 84 "device_type", "cpu", 4); 85 } 86 87 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 88 #define CONFIG_MEM_HOLE_16M 0x1000000 89 /* 90 * Extract hwconfig from environment. 91 * Search for tdm entry in hwconfig. 92 */ 93 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 94 if (ret > 0) 95 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 96 97 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */ 98 if (tdm_hwconfig_enabled) { 99 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE, 100 CONFIG_MEM_HOLE_16M); 101 if (off < 0) 102 printf("Failed to reserve memory for tdm: %s\n", 103 fdt_strerror(off)); 104 } 105 #endif 106 107 /* Reserve the boot page so OSes dont use it */ 108 if ((u64)bootpg < memory_limit) { 109 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 110 if (off < 0) 111 printf("Failed to reserve memory for bootpg: %s\n", 112 fdt_strerror(off)); 113 } 114 115 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR 116 /* 117 * Reserve the default boot page so OSes dont use it. 118 * The default boot page is always mapped to bootpg above using 119 * boot page translation. 120 */ 121 if (0xfffff000ull < memory_limit) { 122 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096); 123 if (off < 0) { 124 printf("Failed to reserve memory for 0xfffff000: %s\n", 125 fdt_strerror(off)); 126 } 127 } 128 #endif 129 130 /* Reserve spin table page */ 131 if (spin_tbl_addr < memory_limit) { 132 off = fdt_add_mem_rsv(blob, 133 (spin_tbl_addr & ~0xffful), 4096); 134 if (off < 0) 135 printf("Failed to reserve memory for spin table: %s\n", 136 fdt_strerror(off)); 137 } 138 #ifdef CONFIG_DEEP_SLEEP 139 #ifdef CONFIG_SPL_MMC_BOOT 140 off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, 141 CONFIG_SYS_MMC_U_BOOT_SIZE); 142 if (off < 0) 143 printf("Failed to reserve memory for SD deep sleep: %s\n", 144 fdt_strerror(off)); 145 #elif defined(CONFIG_SPL_SPI_BOOT) 146 off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, 147 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE); 148 if (off < 0) 149 printf("Failed to reserve memory for SPI deep sleep: %s\n", 150 fdt_strerror(off)); 151 #endif 152 #endif 153 } 154 #endif 155 156 #ifdef CONFIG_SYS_FSL_CPC 157 static inline void ft_fixup_l3cache(void *blob, int off) 158 { 159 u32 line_size, num_ways, size, num_sets; 160 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 161 u32 cfg0 = in_be32(&cpc->cpccfg0); 162 163 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 164 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 165 line_size = CPC_CFG0_LINE_SZ(cfg0); 166 num_sets = size / (line_size * num_ways); 167 168 fdt_setprop(blob, off, "cache-unified", NULL, 0); 169 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 170 fdt_setprop_cell(blob, off, "cache-size", size); 171 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 172 fdt_setprop_cell(blob, off, "cache-level", 3); 173 #ifdef CONFIG_SYS_CACHE_STASHING 174 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 175 #endif 176 } 177 #else 178 #define ft_fixup_l3cache(x, y) 179 #endif 180 181 #if defined(CONFIG_L2_CACHE) 182 /* return size in kilobytes */ 183 static inline u32 l2cache_size(void) 184 { 185 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 186 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 187 u32 ver = SVR_SOC_VER(get_svr()); 188 189 switch (l2siz_field) { 190 case 0x0: 191 break; 192 case 0x1: 193 if (ver == SVR_8540 || ver == SVR_8560 || 194 ver == SVR_8541 || ver == SVR_8555) 195 return 128; 196 else 197 return 256; 198 break; 199 case 0x2: 200 if (ver == SVR_8540 || ver == SVR_8560 || 201 ver == SVR_8541 || ver == SVR_8555) 202 return 256; 203 else 204 return 512; 205 break; 206 case 0x3: 207 return 1024; 208 break; 209 } 210 211 return 0; 212 } 213 214 static inline void ft_fixup_l2cache(void *blob) 215 { 216 int len, off; 217 u32 *ph; 218 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 219 220 const u32 line_size = 32; 221 const u32 num_ways = 8; 222 const u32 size = l2cache_size() * 1024; 223 const u32 num_sets = size / (line_size * num_ways); 224 225 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 226 if (off < 0) { 227 debug("no cpu node fount\n"); 228 return; 229 } 230 231 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 232 233 if (ph == NULL) { 234 debug("no next-level-cache property\n"); 235 return ; 236 } 237 238 off = fdt_node_offset_by_phandle(blob, *ph); 239 if (off < 0) { 240 printf("%s: %s\n", __func__, fdt_strerror(off)); 241 return ; 242 } 243 244 if (cpu) { 245 char buf[40]; 246 247 if (isdigit(cpu->name[0])) { 248 /* MPCxxxx, where xxxx == 4-digit number */ 249 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", 250 cpu->name) + 1; 251 } else { 252 /* Pxxxx or Txxxx, where xxxx == 4-digit number */ 253 len = sprintf(buf, "fsl,%c%s-l2-cache-controller", 254 tolower(cpu->name[0]), cpu->name + 1) + 1; 255 } 256 257 /* 258 * append "cache" after the NULL character that the previous 259 * sprintf wrote. This is how a device tree stores multiple 260 * strings in a property. 261 */ 262 len += sprintf(buf + len, "cache") + 1; 263 264 fdt_setprop(blob, off, "compatible", buf, len); 265 } 266 fdt_setprop(blob, off, "cache-unified", NULL, 0); 267 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 268 fdt_setprop_cell(blob, off, "cache-size", size); 269 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 270 fdt_setprop_cell(blob, off, "cache-level", 2); 271 272 /* we dont bother w/L3 since no platform of this type has one */ 273 } 274 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \ 275 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 276 static inline void ft_fixup_l2cache(void *blob) 277 { 278 int off, l2_off, l3_off = -1; 279 u32 *ph; 280 #ifdef CONFIG_BACKSIDE_L2_CACHE 281 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 282 #else 283 struct ccsr_cluster_l2 *l2cache = 284 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); 285 u32 l2cfg0 = in_be32(&l2cache->l2cfg0); 286 #endif 287 u32 size, line_size, num_ways, num_sets; 288 int has_l2 = 1; 289 290 /* P2040/P2040E has no L2, so dont set any L2 props */ 291 if (SVR_SOC_VER(get_svr()) == SVR_P2040) 292 has_l2 = 0; 293 294 size = (l2cfg0 & 0x3fff) * 64 * 1024; 295 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 296 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 297 num_sets = size / (line_size * num_ways); 298 299 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 300 301 while (off != -FDT_ERR_NOTFOUND) { 302 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 303 304 if (ph == NULL) { 305 debug("no next-level-cache property\n"); 306 goto next; 307 } 308 309 l2_off = fdt_node_offset_by_phandle(blob, *ph); 310 if (l2_off < 0) { 311 printf("%s: %s\n", __func__, fdt_strerror(off)); 312 goto next; 313 } 314 315 if (has_l2) { 316 #ifdef CONFIG_SYS_CACHE_STASHING 317 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 318 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 319 /* Only initialize every eighth thread */ 320 if (reg && !((*reg) % 8)) { 321 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 322 (*reg / 4) + 32 + 1); 323 } 324 #else 325 if (reg) { 326 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 327 (*reg * 2) + 32 + 1); 328 } 329 #endif 330 #endif 331 332 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 333 fdt_setprop_cell(blob, l2_off, "cache-block-size", 334 line_size); 335 fdt_setprop_cell(blob, l2_off, "cache-size", size); 336 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 337 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 338 fdt_setprop(blob, l2_off, "compatible", "cache", 6); 339 } 340 341 if (l3_off < 0) { 342 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 343 344 if (ph == NULL) { 345 debug("no next-level-cache property\n"); 346 goto next; 347 } 348 l3_off = *ph; 349 } 350 next: 351 off = fdt_node_offset_by_prop_value(blob, off, 352 "device_type", "cpu", 4); 353 } 354 if (l3_off > 0) { 355 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 356 if (l3_off < 0) { 357 printf("%s: %s\n", __func__, fdt_strerror(off)); 358 return ; 359 } 360 ft_fixup_l3cache(blob, l3_off); 361 } 362 } 363 #else 364 #define ft_fixup_l2cache(x) 365 #endif 366 367 static inline void ft_fixup_cache(void *blob) 368 { 369 int off; 370 371 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 372 373 while (off != -FDT_ERR_NOTFOUND) { 374 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 375 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 376 u32 isize, iline_size, inum_sets, inum_ways; 377 u32 dsize, dline_size, dnum_sets, dnum_ways; 378 379 /* d-side config */ 380 dsize = (l1cfg0 & 0x7ff) * 1024; 381 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 382 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 383 dnum_sets = dsize / (dline_size * dnum_ways); 384 385 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 386 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 387 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 388 389 #ifdef CONFIG_SYS_CACHE_STASHING 390 { 391 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 392 if (reg) 393 fdt_setprop_cell(blob, off, "cache-stash-id", 394 (*reg * 2) + 32 + 0); 395 } 396 #endif 397 398 /* i-side config */ 399 isize = (l1cfg1 & 0x7ff) * 1024; 400 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 401 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 402 inum_sets = isize / (iline_size * inum_ways); 403 404 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 405 fdt_setprop_cell(blob, off, "i-cache-size", isize); 406 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 407 408 off = fdt_node_offset_by_prop_value(blob, off, 409 "device_type", "cpu", 4); 410 } 411 412 ft_fixup_l2cache(blob); 413 } 414 415 416 void fdt_add_enet_stashing(void *fdt) 417 { 418 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 419 420 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 421 422 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 423 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); 424 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); 425 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); 426 } 427 428 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 429 #ifdef CONFIG_SYS_DPAA_FMAN 430 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 431 unsigned long freq) 432 { 433 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 434 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 435 436 if (off >= 0) { 437 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 438 if (off > 0) 439 printf("WARNING enable to set clock-frequency " 440 "for %s: %s\n", compat, fdt_strerror(off)); 441 } 442 } 443 #endif 444 445 static void ft_fixup_dpaa_clks(void *blob) 446 { 447 sys_info_t sysinfo; 448 449 get_sys_info(&sysinfo); 450 #ifdef CONFIG_SYS_DPAA_FMAN 451 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 452 sysinfo.freq_fman[0]); 453 454 #if (CONFIG_SYS_NUM_FMAN == 2) 455 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 456 sysinfo.freq_fman[1]); 457 #endif 458 #endif 459 460 #ifdef CONFIG_SYS_DPAA_QBMAN 461 do_fixup_by_compat_u32(blob, "fsl,qman", 462 "clock-frequency", sysinfo.freq_qman, 1); 463 #endif 464 465 #ifdef CONFIG_SYS_DPAA_PME 466 do_fixup_by_compat_u32(blob, "fsl,pme", 467 "clock-frequency", sysinfo.freq_pme, 1); 468 #endif 469 } 470 #else 471 #define ft_fixup_dpaa_clks(x) 472 #endif 473 474 #ifdef CONFIG_QE 475 static void ft_fixup_qe_snum(void *blob) 476 { 477 unsigned int svr; 478 479 svr = mfspr(SPRN_SVR); 480 if (SVR_SOC_VER(svr) == SVR_8569) { 481 if(IS_SVR_REV(svr, 1, 0)) 482 do_fixup_by_compat_u32(blob, "fsl,qe", 483 "fsl,qe-num-snums", 46, 1); 484 else 485 do_fixup_by_compat_u32(blob, "fsl,qe", 486 "fsl,qe-num-snums", 76, 1); 487 } 488 } 489 #endif 490 491 /** 492 * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree 493 * 494 * The binding for an Fman firmware node is documented in 495 * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains 496 * the actual Fman firmware binary data. The operating system is expected to 497 * be able to parse the binary data to determine any attributes it needs. 498 */ 499 #ifdef CONFIG_SYS_DPAA_FMAN 500 void fdt_fixup_fman_firmware(void *blob) 501 { 502 int rc, fmnode, fwnode = -1; 503 uint32_t phandle; 504 struct qe_firmware *fmanfw; 505 const struct qe_header *hdr; 506 unsigned int length; 507 uint32_t crc; 508 const char *p; 509 510 /* The first Fman we find will contain the actual firmware. */ 511 fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); 512 if (fmnode < 0) 513 /* Exit silently if there are no Fman devices */ 514 return; 515 516 /* If we already have a firmware node, then also exit silently. */ 517 if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) 518 return; 519 520 /* If the environment variable is not set, then exit silently */ 521 p = getenv("fman_ucode"); 522 if (!p) 523 return; 524 525 fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16); 526 if (!fmanfw) 527 return; 528 529 hdr = &fmanfw->header; 530 length = be32_to_cpu(hdr->length); 531 532 /* Verify the firmware. */ 533 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || 534 (hdr->magic[2] != 'F')) { 535 printf("Data at %p is not an Fman firmware\n", fmanfw); 536 return; 537 } 538 539 if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { 540 printf("Fman firmware at %p is too large (size=%u)\n", 541 fmanfw, length); 542 return; 543 } 544 545 length -= sizeof(u32); /* Subtract the size of the CRC */ 546 crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); 547 if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { 548 printf("Fman firmware at %p has invalid CRC\n", fmanfw); 549 return; 550 } 551 552 /* Increase the size of the fdt to make room for the node. */ 553 rc = fdt_increase_size(blob, fmanfw->header.length); 554 if (rc < 0) { 555 printf("Unable to make room for Fman firmware: %s\n", 556 fdt_strerror(rc)); 557 return; 558 } 559 560 /* Create the firmware node. */ 561 fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); 562 if (fwnode < 0) { 563 char s[64]; 564 fdt_get_path(blob, fmnode, s, sizeof(s)); 565 printf("Could not add firmware node to %s: %s\n", s, 566 fdt_strerror(fwnode)); 567 return; 568 } 569 rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); 570 if (rc < 0) { 571 char s[64]; 572 fdt_get_path(blob, fwnode, s, sizeof(s)); 573 printf("Could not add compatible property to node %s: %s\n", s, 574 fdt_strerror(rc)); 575 return; 576 } 577 phandle = fdt_create_phandle(blob, fwnode); 578 if (!phandle) { 579 char s[64]; 580 fdt_get_path(blob, fwnode, s, sizeof(s)); 581 printf("Could not add phandle property to node %s: %s\n", s, 582 fdt_strerror(rc)); 583 return; 584 } 585 rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); 586 if (rc < 0) { 587 char s[64]; 588 fdt_get_path(blob, fwnode, s, sizeof(s)); 589 printf("Could not add firmware property to node %s: %s\n", s, 590 fdt_strerror(rc)); 591 return; 592 } 593 594 /* Find all other Fman nodes and point them to the firmware node. */ 595 while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { 596 rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); 597 if (rc < 0) { 598 char s[64]; 599 fdt_get_path(blob, fmnode, s, sizeof(s)); 600 printf("Could not add pointer property to node %s: %s\n", 601 s, fdt_strerror(rc)); 602 return; 603 } 604 } 605 } 606 #else 607 #define fdt_fixup_fman_firmware(x) 608 #endif 609 610 #if defined(CONFIG_PPC_P4080) 611 static void fdt_fixup_usb(void *fdt) 612 { 613 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 614 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 615 int off; 616 617 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph"); 618 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) != 619 FSL_CORENET_RCWSR11_EC1_FM1_USB1) 620 fdt_status_disabled(fdt, off); 621 622 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr"); 623 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) != 624 FSL_CORENET_RCWSR11_EC2_USB2) 625 fdt_status_disabled(fdt, off); 626 } 627 #else 628 #define fdt_fixup_usb(x) 629 #endif 630 631 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \ 632 defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) 633 void fdt_fixup_dma3(void *blob) 634 { 635 /* the 3rd DMA is not functional if SRIO2 is chosen */ 636 int nodeoff; 637 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 638 639 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) 640 #if defined(CONFIG_PPC_T2080) 641 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 642 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 643 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 644 645 switch (srds_prtcl_s2) { 646 case 0x29: 647 case 0x2d: 648 case 0x2e: 649 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 650 defined(CONFIG_PPC_T4080) 651 u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & 652 FSL_CORENET2_RCWSR4_SRDS4_PRTCL; 653 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; 654 655 switch (srds_prtcl_s4) { 656 case 6: 657 case 8: 658 case 14: 659 case 16: 660 #endif 661 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma", 662 CONFIG_SYS_ELO3_DMA3); 663 if (nodeoff > 0) 664 fdt_status_disabled(blob, nodeoff); 665 else 666 printf("WARNING: unable to disable dma3\n"); 667 break; 668 default: 669 break; 670 } 671 } 672 #else 673 #define fdt_fixup_dma3(x) 674 #endif 675 676 #if defined(CONFIG_PPC_T1040) 677 static void fdt_fixup_l2_switch(void *blob) 678 { 679 uchar l2swaddr[6]; 680 int node; 681 682 /* The l2switch node from device-tree has 683 * compatible string "vitesse-9953" */ 684 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953"); 685 if (node == -FDT_ERR_NOTFOUND) 686 /* no l2switch node has been found */ 687 return; 688 689 /* Get MAC address for the l2switch from "l2switchaddr"*/ 690 if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) { 691 printf("Warning: MAC address for l2switch not found\n"); 692 memset(l2swaddr, 0, sizeof(l2swaddr)); 693 } 694 695 /* Add MAC address to l2switch node */ 696 fdt_setprop(blob, node, "local-mac-address", l2swaddr, 697 sizeof(l2swaddr)); 698 } 699 #else 700 #define fdt_fixup_l2_switch(x) 701 #endif 702 703 void ft_cpu_setup(void *blob, bd_t *bd) 704 { 705 int off; 706 int val; 707 int len; 708 sys_info_t sysinfo; 709 710 /* delete crypto node if not on an E-processor */ 711 if (!IS_E_PROCESSOR(get_svr())) 712 fdt_fixup_crypto_node(blob, 0); 713 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 714 else { 715 ccsr_sec_t __iomem *sec; 716 717 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 718 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); 719 } 720 #endif 721 722 fdt_fixup_ethernet(blob); 723 724 fdt_add_enet_stashing(blob); 725 726 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV 727 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1 728 #endif 729 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 730 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV, 731 1); 732 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 733 "bus-frequency", bd->bi_busfreq, 1); 734 get_sys_info(&sysinfo); 735 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 736 while (off != -FDT_ERR_NOTFOUND) { 737 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); 738 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]); 739 fdt_setprop(blob, off, "clock-frequency", &val, 4); 740 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 741 "cpu", 4); 742 } 743 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 744 "bus-frequency", bd->bi_busfreq, 1); 745 746 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", 747 "bus-frequency", gd->arch.lbc_clk, 1); 748 do_fixup_by_compat_u32(blob, "fsl,elbc", 749 "bus-frequency", gd->arch.lbc_clk, 1); 750 #ifdef CONFIG_QE 751 ft_qe_setup(blob); 752 ft_fixup_qe_snum(blob); 753 #endif 754 755 fdt_fixup_fman_firmware(blob); 756 757 #ifdef CONFIG_SYS_NS16550 758 do_fixup_by_compat_u32(blob, "ns16550", 759 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 760 #endif 761 762 #ifdef CONFIG_CPM2 763 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 764 "current-speed", gd->baudrate, 1); 765 766 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 767 "clock-frequency", bd->bi_brgfreq, 1); 768 #endif 769 770 #ifdef CONFIG_FSL_CORENET 771 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 772 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 773 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0", 774 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 775 do_fixup_by_compat_u32(blob, "fsl,mpic", 776 "clock-frequency", get_bus_freq(0)/2, 1); 777 #else 778 do_fixup_by_compat_u32(blob, "fsl,mpic", 779 "clock-frequency", get_bus_freq(0), 1); 780 #endif 781 782 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 783 784 #ifdef CONFIG_MP 785 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 786 ft_fixup_num_cores(blob); 787 #endif 788 789 ft_fixup_cache(blob); 790 791 #if defined(CONFIG_FSL_ESDHC) 792 fdt_fixup_esdhc(blob, bd); 793 #endif 794 795 ft_fixup_dpaa_clks(blob); 796 797 #if defined(CONFIG_SYS_BMAN_MEM_PHYS) 798 fdt_portal(blob, "fsl,bman-portal", "bman-portals", 799 (u64)CONFIG_SYS_BMAN_MEM_PHYS, 800 CONFIG_SYS_BMAN_MEM_SIZE); 801 fdt_fixup_bportals(blob); 802 #endif 803 804 #if defined(CONFIG_SYS_QMAN_MEM_PHYS) 805 fdt_portal(blob, "fsl,qman-portal", "qman-portals", 806 (u64)CONFIG_SYS_QMAN_MEM_PHYS, 807 CONFIG_SYS_QMAN_MEM_SIZE); 808 809 fdt_fixup_qportals(blob); 810 #endif 811 812 #ifdef CONFIG_SYS_SRIO 813 ft_srio_setup(blob); 814 #endif 815 816 /* 817 * system-clock = CCB clock/2 818 * Here gd->bus_clk = CCB clock 819 * We are using the system clock as 1588 Timer reference 820 * clock source select 821 */ 822 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", 823 "timer-frequency", gd->bus_clk/2, 1); 824 825 /* 826 * clock-freq should change to clock-frequency and 827 * flexcan-v1.0 should change to p1010-flexcan respectively 828 * in the future. 829 */ 830 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 831 "clock_freq", gd->bus_clk/2, 1); 832 833 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 834 "clock-frequency", gd->bus_clk/2, 1); 835 836 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan", 837 "clock-frequency", gd->bus_clk/2, 1); 838 839 fdt_fixup_usb(blob); 840 841 fdt_fixup_l2_switch(blob); 842 843 fdt_fixup_dma3(blob); 844 } 845 846 /* 847 * For some CCSR devices, we only have the virtual address, not the physical 848 * address. This is because we map CCSR as a whole, so we typically don't need 849 * a macro for the physical address of any device within CCSR. In this case, 850 * we calculate the physical address of that device using it's the difference 851 * between the virtual address of the device and the virtual address of the 852 * beginning of CCSR. 853 */ 854 #define CCSR_VIRT_TO_PHYS(x) \ 855 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) 856 857 static void msg(const char *name, uint64_t uaddr, uint64_t daddr) 858 { 859 printf("Warning: U-Boot configured %s at address %llx,\n" 860 "but the device tree has it at %llx\n", name, uaddr, daddr); 861 } 862 863 /* 864 * Verify the device tree 865 * 866 * This function compares several CONFIG_xxx macros that contain physical 867 * addresses with the corresponding nodes in the device tree, to see if 868 * the physical addresses are all correct. For example, if 869 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address 870 * of the first UART. We convert this to a physical address and compare 871 * that with the physical address of the first ns16550-compatible node 872 * in the device tree. If they don't match, then we display a warning. 873 * 874 * Returns 1 on success, 0 on failure 875 */ 876 int ft_verify_fdt(void *fdt) 877 { 878 uint64_t addr = 0; 879 int aliases; 880 int off; 881 882 /* First check the CCSR base address */ 883 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); 884 if (off > 0) 885 addr = fdt_get_base_address(fdt, off); 886 887 if (!addr) { 888 printf("Warning: could not determine base CCSR address in " 889 "device tree\n"); 890 /* No point in checking anything else */ 891 return 0; 892 } 893 894 if (addr != CONFIG_SYS_CCSRBAR_PHYS) { 895 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); 896 /* No point in checking anything else */ 897 return 0; 898 } 899 900 /* 901 * Check some nodes via aliases. We assume that U-Boot and the device 902 * tree enumerate the devices equally. E.g. the first serial port in 903 * U-Boot is the same as "serial0" in the device tree. 904 */ 905 aliases = fdt_path_offset(fdt, "/aliases"); 906 if (aliases > 0) { 907 #ifdef CONFIG_SYS_NS16550_COM1 908 if (!fdt_verify_alias_address(fdt, aliases, "serial0", 909 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) 910 return 0; 911 #endif 912 913 #ifdef CONFIG_SYS_NS16550_COM2 914 if (!fdt_verify_alias_address(fdt, aliases, "serial1", 915 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) 916 return 0; 917 #endif 918 } 919 920 /* 921 * The localbus node is typically a root node, even though the lbc 922 * controller is part of CCSR. If we were to put the lbc node under 923 * the SOC node, then the 'ranges' property in the lbc node would 924 * translate through the 'ranges' property of the parent SOC node, and 925 * we don't want that. Since it's a separate node, it's possible for 926 * the 'reg' property to be wrong, so check it here. For now, we 927 * only check for "fsl,elbc" nodes. 928 */ 929 #ifdef CONFIG_SYS_LBC_ADDR 930 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); 931 if (off > 0) { 932 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL); 933 if (reg) { 934 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); 935 936 addr = fdt_translate_address(fdt, off, reg); 937 if (uaddr != addr) { 938 msg("the localbus", uaddr, addr); 939 return 0; 940 } 941 } 942 } 943 #endif 944 945 return 1; 946 } 947 948 void fdt_del_diu(void *blob) 949 { 950 int nodeoff = 0; 951 952 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 953 "fsl,diu")) >= 0) { 954 fdt_del_node(blob, nodeoff); 955 } 956 } 957