1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <environment.h> 12 #include <linux/libfdt.h> 13 #include <fdt_support.h> 14 #include <asm/processor.h> 15 #include <linux/ctype.h> 16 #include <asm/io.h> 17 #include <asm/fsl_fdt.h> 18 #include <asm/fsl_portals.h> 19 #include <fsl_qbman.h> 20 #include <hwconfig.h> 21 #ifdef CONFIG_FSL_ESDHC 22 #include <fsl_esdhc.h> 23 #endif 24 #ifdef CONFIG_SYS_DPAA_FMAN 25 #include <fsl_fman.h> 26 #endif 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 extern void ft_qe_setup(void *blob); 31 extern void ft_fixup_num_cores(void *blob); 32 extern void ft_srio_setup(void *blob); 33 34 #ifdef CONFIG_MP 35 #include "mp.h" 36 37 void ft_fixup_cpu(void *blob, u64 memory_limit) 38 { 39 int off; 40 phys_addr_t spin_tbl_addr = get_spin_phys_addr(); 41 u32 bootpg = determine_mp_bootpg(NULL); 42 u32 id = get_my_id(); 43 const char *enable_method; 44 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 45 int ret; 46 int tdm_hwconfig_enabled = 0; 47 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 48 #endif 49 50 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 51 while (off != -FDT_ERR_NOTFOUND) { 52 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 53 54 if (reg) { 55 u32 phys_cpu_id = thread_to_core(*reg); 56 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr; 57 val = cpu_to_fdt64(val); 58 if (*reg == id) { 59 fdt_setprop_string(blob, off, "status", 60 "okay"); 61 } else { 62 fdt_setprop_string(blob, off, "status", 63 "disabled"); 64 } 65 66 if (hold_cores_in_reset(0)) { 67 #ifdef CONFIG_FSL_CORENET 68 /* Cores held in reset, use BRR to release */ 69 enable_method = "fsl,brr-holdoff"; 70 #else 71 /* Cores held in reset, use EEBPCR to release */ 72 enable_method = "fsl,eebpcr-holdoff"; 73 #endif 74 } else { 75 /* Cores out of reset and in a spin-loop */ 76 enable_method = "spin-table"; 77 78 fdt_setprop(blob, off, "cpu-release-addr", 79 &val, sizeof(val)); 80 } 81 82 fdt_setprop_string(blob, off, "enable-method", 83 enable_method); 84 } else { 85 printf ("cpu NULL\n"); 86 } 87 off = fdt_node_offset_by_prop_value(blob, off, 88 "device_type", "cpu", 4); 89 } 90 91 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 92 #define CONFIG_MEM_HOLE_16M 0x1000000 93 /* 94 * Extract hwconfig from environment. 95 * Search for tdm entry in hwconfig. 96 */ 97 ret = env_get_f("hwconfig", buffer, sizeof(buffer)); 98 if (ret > 0) 99 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 100 101 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */ 102 if (tdm_hwconfig_enabled) { 103 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE, 104 CONFIG_MEM_HOLE_16M); 105 if (off < 0) 106 printf("Failed to reserve memory for tdm: %s\n", 107 fdt_strerror(off)); 108 } 109 #endif 110 111 /* Reserve the boot page so OSes dont use it */ 112 if ((u64)bootpg < memory_limit) { 113 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); 114 if (off < 0) 115 printf("Failed to reserve memory for bootpg: %s\n", 116 fdt_strerror(off)); 117 } 118 119 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR 120 /* 121 * Reserve the default boot page so OSes dont use it. 122 * The default boot page is always mapped to bootpg above using 123 * boot page translation. 124 */ 125 if (0xfffff000ull < memory_limit) { 126 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096); 127 if (off < 0) { 128 printf("Failed to reserve memory for 0xfffff000: %s\n", 129 fdt_strerror(off)); 130 } 131 } 132 #endif 133 134 /* Reserve spin table page */ 135 if (spin_tbl_addr < memory_limit) { 136 off = fdt_add_mem_rsv(blob, 137 (spin_tbl_addr & ~0xffful), 4096); 138 if (off < 0) 139 printf("Failed to reserve memory for spin table: %s\n", 140 fdt_strerror(off)); 141 } 142 #ifdef CONFIG_DEEP_SLEEP 143 #ifdef CONFIG_SPL_MMC_BOOT 144 off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, 145 CONFIG_SYS_MMC_U_BOOT_SIZE); 146 if (off < 0) 147 printf("Failed to reserve memory for SD deep sleep: %s\n", 148 fdt_strerror(off)); 149 #elif defined(CONFIG_SPL_SPI_BOOT) 150 off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, 151 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE); 152 if (off < 0) 153 printf("Failed to reserve memory for SPI deep sleep: %s\n", 154 fdt_strerror(off)); 155 #endif 156 #endif 157 } 158 #endif 159 160 #ifdef CONFIG_SYS_FSL_CPC 161 static inline void ft_fixup_l3cache(void *blob, int off) 162 { 163 u32 line_size, num_ways, size, num_sets; 164 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; 165 u32 cfg0 = in_be32(&cpc->cpccfg0); 166 167 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; 168 num_ways = CPC_CFG0_NUM_WAYS(cfg0); 169 line_size = CPC_CFG0_LINE_SZ(cfg0); 170 num_sets = size / (line_size * num_ways); 171 172 fdt_setprop(blob, off, "cache-unified", NULL, 0); 173 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 174 fdt_setprop_cell(blob, off, "cache-size", size); 175 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 176 fdt_setprop_cell(blob, off, "cache-level", 3); 177 #ifdef CONFIG_SYS_CACHE_STASHING 178 fdt_setprop_cell(blob, off, "cache-stash-id", 1); 179 #endif 180 } 181 #else 182 #define ft_fixup_l3cache(x, y) 183 #endif 184 185 #if defined(CONFIG_L2_CACHE) || \ 186 defined(CONFIG_BACKSIDE_L2_CACHE) || \ 187 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 188 static inline void ft_fixup_l2cache_compatible(void *blob, int off) 189 { 190 int len; 191 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); 192 193 if (cpu) { 194 char buf[40]; 195 196 if (isdigit(cpu->name[0])) { 197 /* MPCxxxx, where xxxx == 4-digit number */ 198 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", 199 cpu->name) + 1; 200 } else { 201 /* Pxxxx or Txxxx, where xxxx == 4-digit number */ 202 len = sprintf(buf, "fsl,%c%s-l2-cache-controller", 203 tolower(cpu->name[0]), cpu->name + 1) + 1; 204 } 205 206 /* 207 * append "cache" after the NULL character that the previous 208 * sprintf wrote. This is how a device tree stores multiple 209 * strings in a property. 210 */ 211 len += sprintf(buf + len, "cache") + 1; 212 213 fdt_setprop(blob, off, "compatible", buf, len); 214 } 215 } 216 #endif 217 218 #if defined(CONFIG_L2_CACHE) 219 /* return size in kilobytes */ 220 static inline u32 l2cache_size(void) 221 { 222 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 223 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; 224 u32 ver = SVR_SOC_VER(get_svr()); 225 226 switch (l2siz_field) { 227 case 0x0: 228 break; 229 case 0x1: 230 if (ver == SVR_8540 || ver == SVR_8560 || 231 ver == SVR_8541 || ver == SVR_8555) 232 return 128; 233 else 234 return 256; 235 break; 236 case 0x2: 237 if (ver == SVR_8540 || ver == SVR_8560 || 238 ver == SVR_8541 || ver == SVR_8555) 239 return 256; 240 else 241 return 512; 242 break; 243 case 0x3: 244 return 1024; 245 break; 246 } 247 248 return 0; 249 } 250 251 static inline void ft_fixup_l2cache(void *blob) 252 { 253 int off; 254 u32 *ph; 255 256 const u32 line_size = 32; 257 const u32 num_ways = 8; 258 const u32 size = l2cache_size() * 1024; 259 const u32 num_sets = size / (line_size * num_ways); 260 261 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 262 if (off < 0) { 263 debug("no cpu node fount\n"); 264 return; 265 } 266 267 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 268 269 if (ph == NULL) { 270 debug("no next-level-cache property\n"); 271 return ; 272 } 273 274 off = fdt_node_offset_by_phandle(blob, *ph); 275 if (off < 0) { 276 printf("%s: %s\n", __func__, fdt_strerror(off)); 277 return ; 278 } 279 280 ft_fixup_l2cache_compatible(blob, off); 281 fdt_setprop(blob, off, "cache-unified", NULL, 0); 282 fdt_setprop_cell(blob, off, "cache-block-size", line_size); 283 fdt_setprop_cell(blob, off, "cache-size", size); 284 fdt_setprop_cell(blob, off, "cache-sets", num_sets); 285 fdt_setprop_cell(blob, off, "cache-level", 2); 286 287 /* we dont bother w/L3 since no platform of this type has one */ 288 } 289 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \ 290 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 291 static inline void ft_fixup_l2cache(void *blob) 292 { 293 int off, l2_off, l3_off = -1; 294 u32 *ph; 295 #ifdef CONFIG_BACKSIDE_L2_CACHE 296 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 297 #else 298 struct ccsr_cluster_l2 *l2cache = 299 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); 300 u32 l2cfg0 = in_be32(&l2cache->l2cfg0); 301 #endif 302 u32 size, line_size, num_ways, num_sets; 303 int has_l2 = 1; 304 305 /* P2040/P2040E has no L2, so dont set any L2 props */ 306 if (SVR_SOC_VER(get_svr()) == SVR_P2040) 307 has_l2 = 0; 308 309 size = (l2cfg0 & 0x3fff) * 64 * 1024; 310 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; 311 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; 312 num_sets = size / (line_size * num_ways); 313 314 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 315 316 while (off != -FDT_ERR_NOTFOUND) { 317 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); 318 319 if (ph == NULL) { 320 debug("no next-level-cache property\n"); 321 goto next; 322 } 323 324 l2_off = fdt_node_offset_by_phandle(blob, *ph); 325 if (l2_off < 0) { 326 printf("%s: %s\n", __func__, fdt_strerror(off)); 327 goto next; 328 } 329 330 if (has_l2) { 331 #ifdef CONFIG_SYS_CACHE_STASHING 332 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 333 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 334 /* Only initialize every eighth thread */ 335 if (reg && !((*reg) % 8)) { 336 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 337 (*reg / 4) + 32 + 1); 338 } 339 #else 340 if (reg) { 341 fdt_setprop_cell(blob, l2_off, "cache-stash-id", 342 (*reg * 2) + 32 + 1); 343 } 344 #endif 345 #endif 346 347 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); 348 fdt_setprop_cell(blob, l2_off, "cache-block-size", 349 line_size); 350 fdt_setprop_cell(blob, l2_off, "cache-size", size); 351 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); 352 fdt_setprop_cell(blob, l2_off, "cache-level", 2); 353 ft_fixup_l2cache_compatible(blob, l2_off); 354 } 355 356 if (l3_off < 0) { 357 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); 358 359 if (ph == NULL) { 360 debug("no next-level-cache property\n"); 361 goto next; 362 } 363 l3_off = *ph; 364 } 365 next: 366 off = fdt_node_offset_by_prop_value(blob, off, 367 "device_type", "cpu", 4); 368 } 369 if (l3_off > 0) { 370 l3_off = fdt_node_offset_by_phandle(blob, l3_off); 371 if (l3_off < 0) { 372 printf("%s: %s\n", __func__, fdt_strerror(off)); 373 return ; 374 } 375 ft_fixup_l3cache(blob, l3_off); 376 } 377 } 378 #else 379 #define ft_fixup_l2cache(x) 380 #endif 381 382 static inline void ft_fixup_cache(void *blob) 383 { 384 int off; 385 386 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 387 388 while (off != -FDT_ERR_NOTFOUND) { 389 u32 l1cfg0 = mfspr(SPRN_L1CFG0); 390 u32 l1cfg1 = mfspr(SPRN_L1CFG1); 391 u32 isize, iline_size, inum_sets, inum_ways; 392 u32 dsize, dline_size, dnum_sets, dnum_ways; 393 394 /* d-side config */ 395 dsize = (l1cfg0 & 0x7ff) * 1024; 396 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; 397 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; 398 dnum_sets = dsize / (dline_size * dnum_ways); 399 400 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); 401 fdt_setprop_cell(blob, off, "d-cache-size", dsize); 402 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); 403 404 #ifdef CONFIG_SYS_CACHE_STASHING 405 { 406 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); 407 if (reg) 408 fdt_setprop_cell(blob, off, "cache-stash-id", 409 (*reg * 2) + 32 + 0); 410 } 411 #endif 412 413 /* i-side config */ 414 isize = (l1cfg1 & 0x7ff) * 1024; 415 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; 416 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; 417 inum_sets = isize / (iline_size * inum_ways); 418 419 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); 420 fdt_setprop_cell(blob, off, "i-cache-size", isize); 421 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); 422 423 off = fdt_node_offset_by_prop_value(blob, off, 424 "device_type", "cpu", 4); 425 } 426 427 ft_fixup_l2cache(blob); 428 } 429 430 431 void fdt_add_enet_stashing(void *fdt) 432 { 433 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); 434 435 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); 436 437 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); 438 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); 439 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); 440 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); 441 } 442 443 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) 444 #ifdef CONFIG_SYS_DPAA_FMAN 445 static void ft_fixup_clks(void *blob, const char *compat, u32 offset, 446 unsigned long freq) 447 { 448 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; 449 int off = fdt_node_offset_by_compat_reg(blob, compat, phys); 450 451 if (off >= 0) { 452 off = fdt_setprop_cell(blob, off, "clock-frequency", freq); 453 if (off > 0) 454 printf("WARNING enable to set clock-frequency " 455 "for %s: %s\n", compat, fdt_strerror(off)); 456 } 457 } 458 #endif 459 460 static void ft_fixup_dpaa_clks(void *blob) 461 { 462 sys_info_t sysinfo; 463 464 get_sys_info(&sysinfo); 465 #ifdef CONFIG_SYS_DPAA_FMAN 466 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, 467 sysinfo.freq_fman[0]); 468 469 #if (CONFIG_SYS_NUM_FMAN == 2) 470 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, 471 sysinfo.freq_fman[1]); 472 #endif 473 #endif 474 475 #ifdef CONFIG_SYS_DPAA_QBMAN 476 do_fixup_by_compat_u32(blob, "fsl,qman", 477 "clock-frequency", sysinfo.freq_qman, 1); 478 #endif 479 480 #ifdef CONFIG_SYS_DPAA_PME 481 do_fixup_by_compat_u32(blob, "fsl,pme", 482 "clock-frequency", sysinfo.freq_pme, 1); 483 #endif 484 } 485 #else 486 #define ft_fixup_dpaa_clks(x) 487 #endif 488 489 #ifdef CONFIG_QE 490 static void ft_fixup_qe_snum(void *blob) 491 { 492 unsigned int svr; 493 494 svr = mfspr(SPRN_SVR); 495 if (SVR_SOC_VER(svr) == SVR_8569) { 496 if(IS_SVR_REV(svr, 1, 0)) 497 do_fixup_by_compat_u32(blob, "fsl,qe", 498 "fsl,qe-num-snums", 46, 1); 499 else 500 do_fixup_by_compat_u32(blob, "fsl,qe", 501 "fsl,qe-num-snums", 76, 1); 502 } 503 } 504 #endif 505 506 #if defined(CONFIG_ARCH_P4080) 507 static void fdt_fixup_usb(void *fdt) 508 { 509 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 510 u32 rcwsr11 = in_be32(&gur->rcwsr[11]); 511 int off; 512 513 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph"); 514 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) != 515 FSL_CORENET_RCWSR11_EC1_FM1_USB1) 516 fdt_status_disabled(fdt, off); 517 518 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr"); 519 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) != 520 FSL_CORENET_RCWSR11_EC2_USB2) 521 fdt_status_disabled(fdt, off); 522 } 523 #else 524 #define fdt_fixup_usb(x) 525 #endif 526 527 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \ 528 defined(CONFIG_ARCH_T4160) 529 void fdt_fixup_dma3(void *blob) 530 { 531 /* the 3rd DMA is not functional if SRIO2 is chosen */ 532 int nodeoff; 533 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 534 535 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) 536 #if defined(CONFIG_ARCH_T2080) 537 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 538 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 539 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 540 541 switch (srds_prtcl_s2) { 542 case 0x29: 543 case 0x2d: 544 case 0x2e: 545 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 546 u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & 547 FSL_CORENET2_RCWSR4_SRDS4_PRTCL; 548 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; 549 550 switch (srds_prtcl_s4) { 551 case 6: 552 case 8: 553 case 14: 554 case 16: 555 #endif 556 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma", 557 CONFIG_SYS_ELO3_DMA3); 558 if (nodeoff > 0) 559 fdt_status_disabled(blob, nodeoff); 560 else 561 printf("WARNING: unable to disable dma3\n"); 562 break; 563 default: 564 break; 565 } 566 } 567 #else 568 #define fdt_fixup_dma3(x) 569 #endif 570 571 #if defined(CONFIG_ARCH_T1040) 572 static void fdt_fixup_l2_switch(void *blob) 573 { 574 uchar l2swaddr[6]; 575 int node; 576 577 /* The l2switch node from device-tree has 578 * compatible string "vitesse-9953" */ 579 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953"); 580 if (node == -FDT_ERR_NOTFOUND) 581 /* no l2switch node has been found */ 582 return; 583 584 /* Get MAC address for the l2switch from "l2switchaddr"*/ 585 if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) { 586 printf("Warning: MAC address for l2switch not found\n"); 587 memset(l2swaddr, 0, sizeof(l2swaddr)); 588 } 589 590 /* Add MAC address to l2switch node */ 591 fdt_setprop(blob, node, "local-mac-address", l2swaddr, 592 sizeof(l2swaddr)); 593 } 594 #else 595 #define fdt_fixup_l2_switch(x) 596 #endif 597 598 void ft_cpu_setup(void *blob, bd_t *bd) 599 { 600 int off; 601 int val; 602 int len; 603 sys_info_t sysinfo; 604 605 /* delete crypto node if not on an E-processor */ 606 if (!IS_E_PROCESSOR(get_svr())) 607 fdt_fixup_crypto_node(blob, 0); 608 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 609 else { 610 ccsr_sec_t __iomem *sec; 611 612 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; 613 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); 614 } 615 #endif 616 617 fdt_add_enet_stashing(blob); 618 619 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV 620 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1 621 #endif 622 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 623 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV, 624 1); 625 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, 626 "bus-frequency", bd->bi_busfreq, 1); 627 get_sys_info(&sysinfo); 628 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); 629 while (off != -FDT_ERR_NOTFOUND) { 630 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); 631 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]); 632 fdt_setprop(blob, off, "clock-frequency", &val, 4); 633 off = fdt_node_offset_by_prop_value(blob, off, "device_type", 634 "cpu", 4); 635 } 636 do_fixup_by_prop_u32(blob, "device_type", "soc", 4, 637 "bus-frequency", bd->bi_busfreq, 1); 638 639 #ifdef CONFIG_QE 640 ft_qe_setup(blob); 641 ft_fixup_qe_snum(blob); 642 #endif 643 644 #ifdef CONFIG_SYS_DPAA_FMAN 645 fdt_fixup_fman_firmware(blob); 646 #endif 647 648 #ifdef CONFIG_SYS_NS16550 649 do_fixup_by_compat_u32(blob, "ns16550", 650 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); 651 #endif 652 653 #ifdef CONFIG_CPM2 654 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", 655 "current-speed", gd->baudrate, 1); 656 657 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", 658 "clock-frequency", bd->bi_brgfreq, 1); 659 #endif 660 661 #ifdef CONFIG_FSL_CORENET 662 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", 663 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 664 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0", 665 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); 666 do_fixup_by_compat_u32(blob, "fsl,mpic", 667 "clock-frequency", get_bus_freq(0)/2, 1); 668 #else 669 do_fixup_by_compat_u32(blob, "fsl,mpic", 670 "clock-frequency", get_bus_freq(0), 1); 671 #endif 672 673 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); 674 675 #ifdef CONFIG_MP 676 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); 677 ft_fixup_num_cores(blob); 678 #endif 679 680 ft_fixup_cache(blob); 681 682 #if defined(CONFIG_FSL_ESDHC) 683 fdt_fixup_esdhc(blob, bd); 684 #endif 685 686 ft_fixup_dpaa_clks(blob); 687 688 #if defined(CONFIG_SYS_BMAN_MEM_PHYS) 689 fdt_portal(blob, "fsl,bman-portal", "bman-portals", 690 (u64)CONFIG_SYS_BMAN_MEM_PHYS, 691 CONFIG_SYS_BMAN_MEM_SIZE); 692 fdt_fixup_bportals(blob); 693 #endif 694 695 #if defined(CONFIG_SYS_QMAN_MEM_PHYS) 696 fdt_portal(blob, "fsl,qman-portal", "qman-portals", 697 (u64)CONFIG_SYS_QMAN_MEM_PHYS, 698 CONFIG_SYS_QMAN_MEM_SIZE); 699 700 fdt_fixup_qportals(blob); 701 #endif 702 703 #ifdef CONFIG_SYS_SRIO 704 ft_srio_setup(blob); 705 #endif 706 707 /* 708 * system-clock = CCB clock/2 709 * Here gd->bus_clk = CCB clock 710 * We are using the system clock as 1588 Timer reference 711 * clock source select 712 */ 713 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", 714 "timer-frequency", gd->bus_clk/2, 1); 715 716 /* 717 * clock-freq should change to clock-frequency and 718 * flexcan-v1.0 should change to p1010-flexcan respectively 719 * in the future. 720 */ 721 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 722 "clock_freq", gd->bus_clk/2, 1); 723 724 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", 725 "clock-frequency", gd->bus_clk/2, 1); 726 727 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan", 728 "clock-frequency", gd->bus_clk/2, 1); 729 730 fdt_fixup_usb(blob); 731 732 fdt_fixup_l2_switch(blob); 733 734 fdt_fixup_dma3(blob); 735 } 736 737 /* 738 * For some CCSR devices, we only have the virtual address, not the physical 739 * address. This is because we map CCSR as a whole, so we typically don't need 740 * a macro for the physical address of any device within CCSR. In this case, 741 * we calculate the physical address of that device using it's the difference 742 * between the virtual address of the device and the virtual address of the 743 * beginning of CCSR. 744 */ 745 #define CCSR_VIRT_TO_PHYS(x) \ 746 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) 747 748 static void msg(const char *name, uint64_t uaddr, uint64_t daddr) 749 { 750 printf("Warning: U-Boot configured %s at address %llx,\n" 751 "but the device tree has it at %llx\n", name, uaddr, daddr); 752 } 753 754 /* 755 * Verify the device tree 756 * 757 * This function compares several CONFIG_xxx macros that contain physical 758 * addresses with the corresponding nodes in the device tree, to see if 759 * the physical addresses are all correct. For example, if 760 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address 761 * of the first UART. We convert this to a physical address and compare 762 * that with the physical address of the first ns16550-compatible node 763 * in the device tree. If they don't match, then we display a warning. 764 * 765 * Returns 1 on success, 0 on failure 766 */ 767 int ft_verify_fdt(void *fdt) 768 { 769 uint64_t addr = 0; 770 int aliases; 771 int off; 772 773 /* First check the CCSR base address */ 774 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); 775 if (off > 0) { 776 int size; 777 u32 naddr; 778 const fdt32_t *prop; 779 780 naddr = fdt_address_cells(fdt, off); 781 prop = fdt_getprop(fdt, off, "ranges", &size); 782 addr = fdt_translate_address(fdt, off, prop + naddr); 783 } 784 785 if (!addr) { 786 printf("Warning: could not determine base CCSR address in " 787 "device tree\n"); 788 /* No point in checking anything else */ 789 return 0; 790 } 791 792 if (addr != CONFIG_SYS_CCSRBAR_PHYS) { 793 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); 794 /* No point in checking anything else */ 795 return 0; 796 } 797 798 /* 799 * Check some nodes via aliases. We assume that U-Boot and the device 800 * tree enumerate the devices equally. E.g. the first serial port in 801 * U-Boot is the same as "serial0" in the device tree. 802 */ 803 aliases = fdt_path_offset(fdt, "/aliases"); 804 if (aliases > 0) { 805 #ifdef CONFIG_SYS_NS16550_COM1 806 if (!fdt_verify_alias_address(fdt, aliases, "serial0", 807 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) 808 return 0; 809 #endif 810 811 #ifdef CONFIG_SYS_NS16550_COM2 812 if (!fdt_verify_alias_address(fdt, aliases, "serial1", 813 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) 814 return 0; 815 #endif 816 } 817 818 /* 819 * The localbus node is typically a root node, even though the lbc 820 * controller is part of CCSR. If we were to put the lbc node under 821 * the SOC node, then the 'ranges' property in the lbc node would 822 * translate through the 'ranges' property of the parent SOC node, and 823 * we don't want that. Since it's a separate node, it's possible for 824 * the 'reg' property to be wrong, so check it here. For now, we 825 * only check for "fsl,elbc" nodes. 826 */ 827 #ifdef CONFIG_SYS_LBC_ADDR 828 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); 829 if (off > 0) { 830 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL); 831 if (reg) { 832 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); 833 834 addr = fdt_translate_address(fdt, off, reg); 835 if (uaddr != addr) { 836 msg("the localbus", uaddr, addr); 837 return 0; 838 } 839 } 840 } 841 #endif 842 843 return 1; 844 } 845 846 void fdt_del_diu(void *blob) 847 { 848 int nodeoff = 0; 849 850 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 851 "fsl,diu")) >= 0) { 852 fdt_del_node(blob, nodeoff); 853 } 854 } 855