1 /*
2  * MPC8560 FCC Fast Ethernet
3  * Copyright (c) 2003 Motorola,Inc.
4  * Xianghua Xiao, (X.Xiao@motorola.com)
5  *
6  * Copyright (c) 2000 MontaVista Software, Inc.   Dan Malek (dmalek@jlc.net)
7  *
8  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9  * Marius Groeger <mgroeger@sysgo.de>
10  *
11  * See file CREDITS for list of people who contributed to this
12  * project.
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License as
16  * published by the Free Software Foundation; either version 2 of
17  * the License, or (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27  * MA 02111-1307 USA
28  */
29 
30 /*
31  * MPC8560 FCC Fast Ethernet
32  * Basic ET HW initialization and packet RX/TX routines
33  *
34  * This code will not perform the IO port configuration. This should be
35  * done in the iop_conf_t structure specific for the board.
36  *
37  * TODO:
38  * add a PHY driver to do the negotiation
39  * reflect negotiation results in FPSMR
40  * look for ways to configure the board specific stuff elsewhere, eg.
41  *    config_xxx.h or the board directory
42  */
43 
44 #include <common.h>
45 #include <malloc.h>
46 #include <asm/cpm_85xx.h>
47 #include <command.h>
48 #include <config.h>
49 #include <net.h>
50 
51 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
52 #include <miiphy.h>
53 #endif
54 
55 #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \
56 	defined(CONFIG_NET_MULTI)
57 
58 static struct ether_fcc_info_s
59 {
60 	int ether_index;
61 	int proff_enet;
62 	ulong cpm_cr_enet_sblock;
63 	ulong cpm_cr_enet_page;
64 	ulong cmxfcr_mask;
65 	ulong cmxfcr_value;
66 }
67 	ether_fcc_info[] =
68 {
69 #ifdef CONFIG_ETHER_ON_FCC1
70 {
71 	0,
72 	PROFF_FCC1,
73 	CPM_CR_FCC1_SBLOCK,
74 	CPM_CR_FCC1_PAGE,
75 	CONFIG_SYS_CMXFCR_MASK1,
76 	CONFIG_SYS_CMXFCR_VALUE1
77 },
78 #endif
79 
80 #ifdef CONFIG_ETHER_ON_FCC2
81 {
82 	1,
83 	PROFF_FCC2,
84 	CPM_CR_FCC2_SBLOCK,
85 	CPM_CR_FCC2_PAGE,
86 	CONFIG_SYS_CMXFCR_MASK2,
87 	CONFIG_SYS_CMXFCR_VALUE2
88 },
89 #endif
90 
91 #ifdef CONFIG_ETHER_ON_FCC3
92 {
93 	2,
94 	PROFF_FCC3,
95 	CPM_CR_FCC3_SBLOCK,
96 	CPM_CR_FCC3_PAGE,
97 	CONFIG_SYS_CMXFCR_MASK3,
98 	CONFIG_SYS_CMXFCR_VALUE3
99 },
100 #endif
101 };
102 
103 /*---------------------------------------------------------------------*/
104 
105 /* Maximum input DMA size.  Must be a should(?) be a multiple of 4. */
106 #define PKT_MAXDMA_SIZE         1520
107 
108 /* The FCC stores dest/src/type, data, and checksum for receive packets. */
109 #define PKT_MAXBUF_SIZE         1518
110 #define PKT_MINBUF_SIZE         64
111 
112 /* Maximum input buffer size.  Must be a multiple of 32. */
113 #define PKT_MAXBLR_SIZE         1536
114 
115 #define TOUT_LOOP 1000000
116 
117 #define TX_BUF_CNT 2
118 
119 static uint rxIdx;	/* index of the current RX buffer */
120 static uint txIdx;	/* index of the current TX buffer */
121 
122 /*
123  * FCC Ethernet Tx and Rx buffer descriptors.
124  * Provide for Double Buffering
125  * Note: PKTBUFSRX is defined in net.h
126  */
127 
128 typedef volatile struct rtxbd {
129     cbd_t rxbd[PKTBUFSRX];
130     cbd_t txbd[TX_BUF_CNT];
131 } RTXBD;
132 
133 /*  Good news: the FCC supports external BDs! */
134 #ifdef __GNUC__
135 static RTXBD rtx __attribute__ ((aligned(8)));
136 #else
137 #error "rtx must be 64-bit aligned"
138 #endif
139 
140 #undef ET_DEBUG
141 
142 static int fec_send(struct eth_device* dev, volatile void *packet, int length)
143 {
144     int i = 0;
145     int result = 0;
146 
147     if (length <= 0) {
148 	printf("fec: bad packet size: %d\n", length);
149 	goto out;
150     }
151 
152     for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
153 	if (i >= TOUT_LOOP) {
154 	    printf("fec: tx buffer not ready\n");
155 	    goto out;
156 	}
157     }
158 
159     rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
160     rtx.txbd[txIdx].cbd_datlen = length;
161     rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
162 			       BD_ENET_TX_TC | BD_ENET_TX_PAD);
163 
164     for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
165 	if (i >= TOUT_LOOP) {
166 	    printf("fec: tx error\n");
167 	    goto out;
168 	}
169     }
170 
171 #ifdef ET_DEBUG
172     printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
173     printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
174     for(i=0;i<(length/16 + 1);i++) {
175 	 printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
176     *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
177     *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
178     }
179 #endif
180 
181     /* return only status bits */
182     result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
183     txIdx = (txIdx + 1) % TX_BUF_CNT;
184 
185 out:
186     return result;
187 }
188 
189 static int fec_recv(struct eth_device* dev)
190 {
191     int length;
192 
193     for (;;)
194     {
195 	if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
196 	    length = -1;
197 	    break;     /* nothing received - leave for() loop */
198 	}
199 	length = rtx.rxbd[rxIdx].cbd_datlen;
200 
201 	if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
202 	    printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
203 	}
204 	else {
205 	    /* Pass the packet up to the protocol layers. */
206 	    NetReceive(NetRxPackets[rxIdx], length - 4);
207 	}
208 
209 
210 	/* Give the buffer back to the FCC. */
211 	rtx.rxbd[rxIdx].cbd_datlen = 0;
212 
213 	/* wrap around buffer index when necessary */
214 	if ((rxIdx + 1) >= PKTBUFSRX) {
215 	    rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
216 	    rxIdx = 0;
217 	}
218 	else {
219 	    rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
220 	    rxIdx++;
221 	}
222     }
223     return length;
224 }
225 
226 
227 static int fec_init(struct eth_device* dev, bd_t *bis)
228 {
229     struct ether_fcc_info_s * info = dev->priv;
230     int i;
231     volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
232     volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
233     fcc_enet_t *pram_ptr;
234     unsigned long mem_addr;
235 
236 #if 0
237     mii_discover_phy();
238 #endif
239 
240     /* 28.9 - (1-2): ioports have been set up already */
241 
242     /* 28.9 - (3): connect FCC's tx and rx clocks */
243     cpm->im_cpm_mux.cmxuar = 0; /* ATM */
244     cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
245 							info->cmxfcr_value;
246 
247     /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
248     if(info->ether_index == 0) {
249 	cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
250     } else if (info->ether_index == 1) {
251 	cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
252     } else if (info->ether_index == 2) {
253 	cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
254     }
255 
256     /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
257     if(info->ether_index == 0) {
258 	cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
259     } else if (info->ether_index == 1){
260 	cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
261     } else if (info->ether_index == 2){
262 	cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
263     }
264 
265     /* 28.9 - (6): FDSR: Ethernet Syn */
266     if(info->ether_index == 0) {
267 	cpm->im_cpm_fcc1.fdsr = 0xD555;
268     } else if (info->ether_index == 1) {
269 	cpm->im_cpm_fcc2.fdsr = 0xD555;
270     } else if (info->ether_index == 2) {
271 	cpm->im_cpm_fcc3.fdsr = 0xD555;
272     }
273 
274     /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
275     rxIdx = 0;
276     txIdx = 0;
277 
278     /* Setup Receiver Buffer Descriptors */
279     for (i = 0; i < PKTBUFSRX; i++)
280     {
281       rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
282       rtx.rxbd[i].cbd_datlen = 0;
283       rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
284     }
285     rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
286 
287     /* Setup Ethernet Transmitter Buffer Descriptors */
288     for (i = 0; i < TX_BUF_CNT; i++)
289     {
290       rtx.txbd[i].cbd_sc = 0;
291       rtx.txbd[i].cbd_datlen = 0;
292       rtx.txbd[i].cbd_bufaddr = 0;
293     }
294     rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
295 
296     /* 28.9 - (7): initialize parameter ram */
297     pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
298 
299     /* clear whole structure to make sure all reserved fields are zero */
300     memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
301 
302     /*
303      * common Parameter RAM area
304      *
305      * Allocate space in the reserved FCC area of DPRAM for the
306      * internal buffers.  No one uses this space (yet), so we
307      * can do this.  Later, we will add resource management for
308      * this area.
309      * CPM_FCC_SPECIAL_BASE:	0xB000 for MPC8540, MPC8560
310      *				0x9000 for MPC8541, MPC8555
311      */
312     mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
313     pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
314     pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
315     /*
316      * Set maximum bytes per receive buffer.
317      * It must be a multiple of 32.
318      */
319     pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
320     /* localbus SDRAM should be preferred */
321     pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
322 				       CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
323     pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
324     pram_ptr->fen_genfcc.fcc_rbdstat = 0;
325     pram_ptr->fen_genfcc.fcc_rbdlen = 0;
326     pram_ptr->fen_genfcc.fcc_rdptr = 0;
327     /* localbus SDRAM should be preferred */
328     pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
329 				       CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
330     pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
331     pram_ptr->fen_genfcc.fcc_tbdstat = 0;
332     pram_ptr->fen_genfcc.fcc_tbdlen = 0;
333     pram_ptr->fen_genfcc.fcc_tdptr = 0;
334 
335     /* protocol-specific area */
336     pram_ptr->fen_statbuf = 0x0;
337     pram_ptr->fen_cmask = 0xdebb20e3;	/* CRC mask */
338     pram_ptr->fen_cpres = 0xffffffff;	/* CRC preset */
339     pram_ptr->fen_crcec = 0;
340     pram_ptr->fen_alec = 0;
341     pram_ptr->fen_disfc = 0;
342     pram_ptr->fen_retlim = 15;		/* Retry limit threshold */
343     pram_ptr->fen_retcnt = 0;
344     pram_ptr->fen_pper = 0;
345     pram_ptr->fen_boffcnt = 0;
346     pram_ptr->fen_gaddrh = 0;
347     pram_ptr->fen_gaddrl = 0;
348     pram_ptr->fen_mflr = PKT_MAXBUF_SIZE;   /* maximum frame length register */
349     /*
350      * Set Ethernet station address.
351      *
352      * This is supplied in the board information structure, so we
353      * copy that into the controller.
354      * So far we have only been given one Ethernet address. We make
355      * it unique by setting a few bits in the upper byte of the
356      * non-static part of the address.
357      */
358 #define ea eth_get_dev()->enetaddr
359     pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
360     pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
361     pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
362 #undef ea
363     pram_ptr->fen_ibdcount = 0;
364     pram_ptr->fen_ibdstart = 0;
365     pram_ptr->fen_ibdend = 0;
366     pram_ptr->fen_txlen = 0;
367     pram_ptr->fen_iaddrh = 0;  /* disable hash */
368     pram_ptr->fen_iaddrl = 0;
369     pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
370     /* pad pointer. use tiptr since we don't need a specific padding char */
371     pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
372     pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE;	/* maximum DMA1 length:1520 */
373     pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE;	/* maximum DMA2 length:1520 */
374 
375 #if defined(ET_DEBUG)
376     printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
377     printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
378 	pram_ptr->fen_genfcc.fcc_rbase);
379     printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
380 	pram_ptr->fen_genfcc.fcc_tbase);
381 #endif
382 
383     /* 28.9 - (8)(9): clear out events in FCCE */
384     /* 28.9 - (9): FCCM: mask all events */
385     if(info->ether_index == 0) {
386 	cpm->im_cpm_fcc1.fcce = ~0x0;
387 	cpm->im_cpm_fcc1.fccm = 0;
388     } else if (info->ether_index == 1) {
389 	cpm->im_cpm_fcc2.fcce = ~0x0;
390 	cpm->im_cpm_fcc2.fccm = 0;
391     } else if (info->ether_index == 2) {
392 	cpm->im_cpm_fcc3.fcce = ~0x0;
393 	cpm->im_cpm_fcc3.fccm = 0;
394     }
395 
396     /* 28.9 - (10-12): we don't use ethernet interrupts */
397 
398     /* 28.9 - (13)
399      *
400      * Let's re-initialize the channel now.  We have to do it later
401      * than the manual describes because we have just now finished
402      * the BD initialization.
403      */
404     cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
405 			    info->cpm_cr_enet_sblock,
406 			    0x0c,
407 			    CPM_CR_INIT_TRX) | CPM_CR_FLG;
408     do {
409 	__asm__ __volatile__ ("eieio");
410     } while (cp->cpcr & CPM_CR_FLG);
411 
412     /* 28.9 - (14): enable tx/rx in gfmr */
413     if(info->ether_index == 0) {
414 	cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
415     } else if (info->ether_index == 1) {
416 	cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
417     } else if (info->ether_index == 2) {
418 	cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
419     }
420 
421     return 1;
422 }
423 
424 static void fec_halt(struct eth_device* dev)
425 {
426     struct ether_fcc_info_s * info = dev->priv;
427     volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
428 
429     /* write GFMR: disable tx/rx */
430     if(info->ether_index == 0) {
431 	cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
432     } else if(info->ether_index == 1) {
433 	cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
434     } else if(info->ether_index == 2) {
435 	cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
436     }
437 }
438 
439 int fec_initialize(bd_t *bis)
440 {
441 	struct eth_device* dev;
442 	int i;
443 
444 	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
445 	{
446 		dev = (struct eth_device*) malloc(sizeof *dev);
447 		memset(dev, 0, sizeof *dev);
448 
449 		sprintf(dev->name, "FCC%d",
450 			ether_fcc_info[i].ether_index + 1);
451 		dev->priv   = &ether_fcc_info[i];
452 		dev->init   = fec_init;
453 		dev->halt   = fec_halt;
454 		dev->send   = fec_send;
455 		dev->recv   = fec_recv;
456 
457 		eth_register(dev);
458 
459 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
460 		&& defined(CONFIG_BITBANGMII)
461 		miiphy_register(dev->name,
462 				bb_miiphy_read,	bb_miiphy_write);
463 #endif
464 	}
465 
466 	return 1;
467 }
468 
469 #endif
470