1 /*
2  * Copyright 2009-2012 Freescale Semiconductor, Inc
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/processor.h>
9 #include <asm/mmu.h>
10 #include <asm/fsl_law.h>
11 #include <asm/io.h>
12 
13 DECLARE_GLOBAL_DATA_PTR;
14 
15 #ifdef CONFIG_A003399_NOR_WORKAROUND
16 void setup_ifc(void)
17 {
18 	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
19 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
20 	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
21 
22 	/*
23 	 * Adjust the TLB we were running out of to match the phys addr of the
24 	 * chip select we are adjusting and will return to.
25 	 */
26 	flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
27 
28 	_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
29 	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
30 			MAS1_TSIZE(BOOKE_PAGESZ_4M);
31 	_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
32 	_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
33 	_mas7 = FSL_BOOKE_MAS7(flash_phys);
34 
35 	mtspr(MAS0, _mas0);
36 	mtspr(MAS1, _mas1);
37 	mtspr(MAS2, _mas2);
38 	mtspr(MAS3, _mas3);
39 	mtspr(MAS7, _mas7);
40 
41 	asm volatile("isync;msync;tlbwe;isync");
42 
43 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
44 /*
45  * TLB entry for debuggging in AS1
46  * Create temporary TLB entry in AS0 to handle debug exception
47  * As on debug exception MSR is cleared i.e. Address space is changed
48  * to 0. A TLB entry (in AS0) is required to handle debug exception generated
49  * in AS1.
50  *
51  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
52  * bacause flash's physical address is going to change as
53  * CONFIG_SYS_FLASH_BASE_PHYS.
54  */
55 	_mas0 = MAS0_TLBSEL(1) |
56 			MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
57 	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
58 			MAS1_TSIZE(BOOKE_PAGESZ_4M);
59 	_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
60 	_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
61 	_mas7 = FSL_BOOKE_MAS7(flash_phys);
62 
63 	mtspr(MAS0, _mas0);
64 	mtspr(MAS1, _mas1);
65 	mtspr(MAS2, _mas2);
66 	mtspr(MAS3, _mas3);
67 	mtspr(MAS7, _mas7);
68 
69 	asm volatile("isync;msync;tlbwe;isync");
70 #endif
71 
72 	/* Change flash's physical address */
73 	out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
74 	out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
75 	out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
76 
77 	return ;
78 }
79 #endif
80 
81 /* We run cpu_init_early_f in AS = 1 */
82 void cpu_init_early_f(void)
83 {
84 	u32 mas0, mas1, mas2, mas3, mas7;
85 	int i;
86 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
87 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
88 #endif
89 #ifdef CONFIG_A003399_NOR_WORKAROUND
90 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
91 	u32  *dst, *src;
92 	void (*setup_ifc_sram)(void);
93 #endif
94 
95 	/* Pointer is writable since we allocated a register for it */
96 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
97 
98 	/*
99 	 * Clear initial global data
100 	 *   we don't use memset so we can share this code with NAND_SPL
101 	 */
102 	for (i = 0; i < sizeof(gd_t); i++)
103 		((char *)gd)[i] = 0;
104 
105 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
106 	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
107 	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
108 	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
109 	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
110 
111 	write_tlb(mas0, mas1, mas2, mas3, mas7);
112 
113 /*
114  * Work Around for IFC Erratum A-003549. This issue is P1010
115  * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
116  * Hence specifically selecting CS3.
117  */
118 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
119 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
120 #endif
121 
122 	init_laws();
123 
124 /*
125  * Work Around for IFC Erratum A003399, issue will hit only when execution
126  * from NOR Flash
127  */
128 #ifdef CONFIG_A003399_NOR_WORKAROUND
129 #define SRAM_BASE_ADDR	(0x00000000)
130 	/* TLB for SRAM */
131 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
132 	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
133 		MAS1_TSIZE(BOOKE_PAGESZ_1M);
134 	mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
135 	mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
136 	mas7 = FSL_BOOKE_MAS7(0);
137 
138 	write_tlb(mas0, mas1, mas2, mas3, mas7);
139 
140 	out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
141 
142 	out_be32(&l2cache->l2errdis,
143 		(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
144 
145 	out_be32(&l2cache->l2ctl,
146 		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
147 
148 	/*
149 	 * Copy the code in setup_ifc to L2SRAM. Do a word copy
150 	 * because NOR Flash on P1010 does not support byte
151 	 * access (Erratum IFC-A002769)
152 	 */
153 	setup_ifc_sram = (void *)SRAM_BASE_ADDR;
154 	dst = (u32 *) SRAM_BASE_ADDR;
155 	src = (u32 *) setup_ifc;
156 	for (i = 0; i < 1024; i++)
157 		*dst++ = *src++;
158 
159 	setup_ifc_sram();
160 
161 	/* CLEANUP */
162 	clrbits_be32(&l2cache->l2ctl,
163 			(MPC85xx_L2CTL_L2E |
164 			 MPC85xx_L2CTL_L2SRAM_ENTIRE));
165 	out_be32(&l2cache->l2srbar0, 0x0);
166 #endif
167 
168 	invalidate_tlb(1);
169 
170 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
171 	!(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
172 	!defined(CONFIG_NAND_SPL)
173 	disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
174 #endif
175 
176 	init_tlbs();
177 }
178