1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2009-2012 Freescale Semiconductor, Inc
4  */
5 
6 #include <common.h>
7 #include <asm/processor.h>
8 #include <asm/mmu.h>
9 #include <asm/fsl_law.h>
10 #include <asm/io.h>
11 
12 DECLARE_GLOBAL_DATA_PTR;
13 
14 #ifdef CONFIG_A003399_NOR_WORKAROUND
15 void setup_ifc(void)
16 {
17 	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
18 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
19 	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
20 
21 	/*
22 	 * Adjust the TLB we were running out of to match the phys addr of the
23 	 * chip select we are adjusting and will return to.
24 	 */
25 	flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
26 
27 	_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
28 	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
29 			MAS1_TSIZE(BOOKE_PAGESZ_4M);
30 	_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
31 	_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
32 	_mas7 = FSL_BOOKE_MAS7(flash_phys);
33 
34 	mtspr(MAS0, _mas0);
35 	mtspr(MAS1, _mas1);
36 	mtspr(MAS2, _mas2);
37 	mtspr(MAS3, _mas3);
38 	mtspr(MAS7, _mas7);
39 
40 	asm volatile("isync;msync;tlbwe;isync");
41 
42 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
43 /*
44  * TLB entry for debuggging in AS1
45  * Create temporary TLB entry in AS0 to handle debug exception
46  * As on debug exception MSR is cleared i.e. Address space is changed
47  * to 0. A TLB entry (in AS0) is required to handle debug exception generated
48  * in AS1.
49  *
50  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
51  * bacause flash's physical address is going to change as
52  * CONFIG_SYS_FLASH_BASE_PHYS.
53  */
54 	_mas0 = MAS0_TLBSEL(1) |
55 			MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
56 	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
57 			MAS1_TSIZE(BOOKE_PAGESZ_4M);
58 	_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
59 	_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
60 	_mas7 = FSL_BOOKE_MAS7(flash_phys);
61 
62 	mtspr(MAS0, _mas0);
63 	mtspr(MAS1, _mas1);
64 	mtspr(MAS2, _mas2);
65 	mtspr(MAS3, _mas3);
66 	mtspr(MAS7, _mas7);
67 
68 	asm volatile("isync;msync;tlbwe;isync");
69 #endif
70 
71 	/* Change flash's physical address */
72 	ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
73 	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
74 	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
75 
76 	return ;
77 }
78 #endif
79 
80 /* We run cpu_init_early_f in AS = 1 */
81 void cpu_init_early_f(void *fdt)
82 {
83 	u32 mas0, mas1, mas2, mas3, mas7;
84 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
85 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
86 #endif
87 #ifdef CONFIG_A003399_NOR_WORKAROUND
88 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
89 	u32  *dst, *src;
90 	void (*setup_ifc_sram)(void);
91 	int i;
92 #endif
93 
94 	/* Pointer is writable since we allocated a register for it */
95 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
96 
97 	/* gd area was zeroed during startup */
98 
99 #ifdef CONFIG_ARCH_QEMU_E500
100 	/*
101 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
102 	 * so we need to populate it before it accesses it.
103 	 */
104 	gd->fdt_blob = fdt;
105 #endif
106 
107 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
108 	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
109 	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
110 	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
111 	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
112 
113 	write_tlb(mas0, mas1, mas2, mas3, mas7);
114 
115 /*
116  * Work Around for IFC Erratum A-003549. This issue is P1010
117  * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
118  * Hence specifically selecting CS3.
119  */
120 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
121 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
122 #endif
123 
124 	init_laws();
125 
126 /*
127  * Work Around for IFC Erratum A003399, issue will hit only when execution
128  * from NOR Flash
129  */
130 #ifdef CONFIG_A003399_NOR_WORKAROUND
131 #define SRAM_BASE_ADDR	(0x00000000)
132 	/* TLB for SRAM */
133 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
134 	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
135 		MAS1_TSIZE(BOOKE_PAGESZ_1M);
136 	mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
137 	mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
138 	mas7 = FSL_BOOKE_MAS7(0);
139 
140 	write_tlb(mas0, mas1, mas2, mas3, mas7);
141 
142 	out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
143 
144 	out_be32(&l2cache->l2errdis,
145 		(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
146 
147 	out_be32(&l2cache->l2ctl,
148 		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
149 
150 	/*
151 	 * Copy the code in setup_ifc to L2SRAM. Do a word copy
152 	 * because NOR Flash on P1010 does not support byte
153 	 * access (Erratum IFC-A002769)
154 	 */
155 	setup_ifc_sram = (void *)SRAM_BASE_ADDR;
156 	dst = (u32 *) SRAM_BASE_ADDR;
157 	src = (u32 *) setup_ifc;
158 	for (i = 0; i < 1024; i++) {
159 		/* cppcheck-suppress nullPointer */
160 		*dst++ = *src++;
161 	}
162 
163 	/* cppcheck-suppress nullPointer */
164 	setup_ifc_sram();
165 
166 	/* CLEANUP */
167 	clrbits_be32(&l2cache->l2ctl,
168 			(MPC85xx_L2CTL_L2E |
169 			 MPC85xx_L2CTL_L2SRAM_ENTIRE));
170 	out_be32(&l2cache->l2srbar0, 0x0);
171 #endif
172 
173 	invalidate_tlb(1);
174 
175 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
176 	!(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
177 	!defined(CONFIG_NAND_SPL)
178 	disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
179 #endif
180 
181 	init_tlbs();
182 }
183