1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <asm/processor.h> 22 #include <asm/mmu.h> 23 #include <asm/fsl_law.h> 24 #include <asm/io.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) 29 void setup_ifc(void) 30 { 31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 32 u32 _mas0, _mas1, _mas2, _mas3, _mas7; 33 phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; 34 35 /* 36 * Adjust the TLB we were running out of to match the phys addr of the 37 * chip select we are adjusting and will return to. 38 */ 39 flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; 40 41 _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); 42 _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | 43 MAS1_TSIZE(BOOKE_PAGESZ_4M); 44 _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); 45 _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); 46 _mas7 = FSL_BOOKE_MAS7(flash_phys); 47 48 mtspr(MAS0, _mas0); 49 mtspr(MAS1, _mas1); 50 mtspr(MAS2, _mas2); 51 mtspr(MAS3, _mas3); 52 mtspr(MAS7, _mas7); 53 54 asm volatile("isync;msync;tlbwe;isync"); 55 56 out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); 57 out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); 58 out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); 59 60 return ; 61 } 62 #endif 63 64 /* We run cpu_init_early_f in AS = 1 */ 65 void cpu_init_early_f(void) 66 { 67 u32 mas0, mas1, mas2, mas3, mas7; 68 int i; 69 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 70 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 71 #endif 72 #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) 73 ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 74 u32 *l2srbar, *dst, *src; 75 void (*setup_ifc_sram)(void); 76 #endif 77 78 /* Pointer is writable since we allocated a register for it */ 79 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 80 81 /* 82 * Clear initial global data 83 * we don't use memset so we can share this code with NAND_SPL 84 */ 85 for (i = 0; i < sizeof(gd_t); i++) 86 ((char *)gd)[i] = 0; 87 88 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); 89 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); 90 mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); 91 mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); 92 mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); 93 94 write_tlb(mas0, mas1, mas2, mas3, mas7); 95 96 /* 97 * Work Around for IFC Erratum A-003549. This issue is P1010 98 * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC 99 * Hence specifically selecting CS3. 100 */ 101 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 102 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); 103 #endif 104 105 init_laws(); 106 107 /* 108 * Work Around for IFC Erratum A003399, issue will hit only when execution 109 * from NOR Flash 110 */ 111 #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) 112 #define SRAM_BASE_ADDR (0x00000000) 113 /* TLB for SRAM */ 114 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9); 115 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | 116 MAS1_TSIZE(BOOKE_PAGESZ_1M); 117 mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I); 118 mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR); 119 mas7 = FSL_BOOKE_MAS7(0); 120 121 write_tlb(mas0, mas1, mas2, mas3, mas7); 122 123 out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); 124 125 out_be32(&l2cache->l2errdis, 126 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); 127 128 out_be32(&l2cache->l2ctl, 129 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); 130 131 /* 132 * Copy the code in setup_ifc to L2SRAM. Do a word copy 133 * because NOR Flash on P1010 does not support byte 134 * access (Erratum IFC-A002769) 135 */ 136 setup_ifc_sram = (void *)SRAM_BASE_ADDR; 137 dst = (u32 *) SRAM_BASE_ADDR; 138 src = (u32 *) setup_ifc; 139 for (i = 0; i < 1024; i++) 140 *l2srbar++ = *src++; 141 142 setup_ifc_sram(); 143 144 /* CLEANUP */ 145 clrbits_be32(&l2cache->l2ctl, 146 (MPC85xx_L2CTL_L2E | 147 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 148 out_be32(&l2cache->l2srbar0, 0x0); 149 #endif 150 151 invalidate_tlb(1); 152 153 #if defined(CONFIG_SECURE_BOOT) 154 /* Disable the TLBs created by ISBC */ 155 for (i = CONFIG_SYS_ISBC_START_TLB; 156 i < CONFIG_SYS_ISBC_START_TLB + CONFIG_SYS_ISBC_NUM_TLBS; i++) 157 disable_tlb(i); 158 #endif 159 160 init_tlbs(); 161 } 162